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1.
This paper presents a simple and accurate nonlinear four-terminal floating nullor (FTFN) macromodel. The FTFN characteristics are simulated by using the new macromodel and are compared with the simulation results obtained by SPICE device models. The results show that the proposed FTFN macromodel represents the CMOS FTFN with approximately the same accuracy as semiconductor SPICE device models but with a significantly reduced computer time.  相似文献   

2.
An accurate CMOS process independent propagation delay macromodel is presented for inverter and multiple input NAND and NOR gates. A new nonsymmetrical input dependent delay model is shown to improve delay estimation accuracy. CMOS process independence is achieved without the application of recurrent data fitting techniques  相似文献   

3.
This paper presents a new methodology for automated broadband model generation from S-parameter data for interconnects and passive components. The new methodology is based on augmenting an existing equivalent circuit model with a macromodel (black-box) network described by rational functions while simultaneously perturbing the equivalent circuit component values. The macromodel network is determined using standard least-squares or vector-fitting approaches. The perturbation of the equivalent circuit parameter values is achieved during the macromodel generation by means of global optimization based on intelligent search algorithms. The new approach is demonstrated on several two-port test example structures including a broadband probe tip structure and a CMOS spiral inductor.  相似文献   

4.
This paper presents a systematic analysis to determine the tuning range limitations of biquadratic OTAC filter architectures, as well as a strategy for the selection of minimum parasitic effects filter structures for a given transfer function (filter type). The analysis uses an OTA macromodel that includes finite input and output impedances along with frequency-dependent transconductance. Experimental data of the macromodel parameters of real OTAs along with analytical results are used to estimate the practical tuning (bounds) limitations of the different biquadratic filter structures. Some of the available transfer functions from these filter architectures present minimum parasitic effects. Experimental results from CMOS chip tests showed agreement with the minimum parasitic effects theoretical results.  相似文献   

5.
Digital noise in mixed-signal circuits is characterized using a scalable macromodel for substrate noise coupling. The noise coupling obtained through simulations is verified with measured data from a digital noise generator and noise sensitive analog circuits fabricated in the 0.35-/spl mu/m heavily doped CMOS process. The simulations and measurements also demonstrate the effectiveness of including grounded guard rings and separating bulk and supply pins in digital circuits to reduce substrate coupling.  相似文献   

6.
Nonzero signal rise and fall times significantly contribute to gate propagation delay. Designers must accurately consider them when defining timing library format. Based on a design oriented macromodel of the timing performance of complementary metal-oxide semiconductor (CMOS) structures, a general representation of transition times allowing fast and accurate cell performance evaluation is presented. This representation is validated comparing calculated gate input-output transition time values with respect to standard lookup representation obtained from HSPICE simulations (BSIM3, v.3, level 69, 0.25 μm process)  相似文献   

7.
深亚微米Sigma-Delta ADC设计方法研究   总被引:1,自引:1,他引:0  
通过一个0.18μm CMOS工艺、低功耗Sigma-Delta ADC调制器(SDM)部分的设计研究,提出了一种深亚微米下混合信号处理系统的设计方法,论述了从系统级行为验证到电路级验证的设计流程,与传统流程相比,在行为级验证中采用了SIMULINK建模方法,在电路级的验证中,提出了从宏模型验证到晶体管级细电路验证这样一种新颖的设计方案,其中所提出的宏模型以6.5%的仿真时间获得97.5%的仿真精度,晶体管级电路以此指标设计,确保其一次验证通过,提高了系统设计效率。  相似文献   

8.
A macromodel for integrated-circuit comparators, suitable for use with typical present-day (1976) circuit simulators, is presented. The macromodel can provide up to an order of magnitude reduction in CPU time and matrix size for CAD. Good agreement (typically within 10 percent) between experimental and macromodel transient response parameters is obtained. A detailed macromodel design procedure is presented that enables the macromodel parameters to be found from typical data-sheet or easily-measured parameters.  相似文献   

9.
A simpler macromodel than that proposed by G. Boyle et al. (1974) is presented. This macromodel does, however, include a large number of operational amplifier characteristics. Advantages of this macromodel include: it is simpler, it is always feasible to calculate parameters, it can be more suitable for AC analysis, and it is quicker to simulate. For the given circuits, the DC analysis with this macromodel was about four times shorter than with the Weil-McNamee (1978) and about two and a half times shorter than with the macromodel of Boyle et al. The duration of transient analysis was up to seven times shorter with the new macromodel than with the Weil-McNamee model, and up to 50% shorter than with the Boyle et al. macromodel  相似文献   

10.
This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 μm CMOS process. Applications of the model to circuit design are demonstrated with simulation results  相似文献   

11.
In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the ft and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.  相似文献   

12.
An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required for macromodel definition. A five-stage ring oscillator is computer simulated to demonstrate the application of the macromodel. Lateral current transfer (LCT) between adjacent gates and injector current redistribution (ICR) effects are shown to reduce gate propagation delay times. When both effects are included, the macromodel produces an agreement between computer simulated and experimental results of better than 10 percent. A ring oscillator example illustrates the use of the macromodel to provide physical insight into the layout sensitivity of I/SUP 2/L.  相似文献   

13.
介绍互补金属氧化物半导体(CMOS)集成电路的发展历程及纳米级CMOS集成电路的关键技术,在此基础上研究了纳米级CMOS集成电路的辐射效应及辐射加固现状。研究结果表明,纳米级FDSOICMOS集成电路无需特殊的加固措施,却比相同技术代的体硅CMOS集成电路有好得多的辐射加固能力,特别适用于空间应用环境。  相似文献   

14.
本文提出了一个由构造法建立的模拟乘法器的宏模型,该模型可以模拟乘法器的动态特性、静态特性与非线性特性的十几种特性参数,并且电路简单,是一个比较全面而实用的模型。  相似文献   

15.
F-I类比方法及MEMS梁的等效电路宏模型   总被引:1,自引:0,他引:1  
建立了一种基于力-电流( F- I)类比、适用于梁结构机电耦合系统小信号时域及频域分析的等效电路宏模型,与已有的基于力-电压( F- V)类比的等效电路宏模型相比,基于F- I类比的等效电路宏模型的电网络与原来的机械网络具有相同的拓扑结构,因此,基于F- I类比的等效电路宏模型能为复杂机电系统等效电路宏模型的建立带来很大的方便.模拟结果表明该模型具有较高的精度.  相似文献   

16.
A general-purpose nonlinear macromodel for the time-domain simulation of integrated circuit operational amplifiers (op amps), either bipolar or MOS, is presented. Three main differences exist between the macromodel and those previously reported in the literature for the time domain. First, all the op-amp nonlinearities are simulated using threshold elements and digital components, thus making them well suited for a mixed electrical/logical simulator. Secondly, the macromodel exhibits a superior performance in those cases where the op amp is driven by a large signal. Finally, the macromodel is advantageous in terms of CPU time. Several examples are included illustrating all of these advantages. The main application of this macromodel is for the accurate simulation of the analog part of a combined analog/digital integrated circuit  相似文献   

17.
考虑微磁芯磁阻的分布参数微梁执行器小信号宏模型   总被引:1,自引:1,他引:0  
以多级弯曲磁微梁执行器为研究对象,先采用梁的模态函数线性组合来逼近梁的变形曲线,然后利用磁路定律,考虑了在宏观磁执行器中忽略的磁芯磁阻,建立了考虑力-磁耦合的非线性方程组,克服了以往的磁微执行器模型不能考虑力磁耦合,而且忽略磁芯磁阻的缺点.计算结果与实验数据及有限元计算结果对比表明,文中的模型有足够的精度,可以作为宏模型使用.  相似文献   

18.
In this paper a new electrothermal compact macromodel of the monolithic switching voltage regulator MC34063A for SPICE is proposed. This macromodel, valid for the transient analysis, is composed of two essential parts: the electrical model consisting of the most important fundamental blocks as: the oscillator, the comparator, the RS flip-flop, the output stage as well as the lumped thermal model. The correctness of the macromodel is verified experimentally. The values of the macromodel parameters are determined from the measurements and the catalogue data. Some of the calculated characteristics are compared with the measuring results.  相似文献   

19.
A macromodel for integrated all-MOS operational amplifiers is developed with reference to circuits where the settling behavior of the op amps is of particular concern. Expressions for the values of the elements of the macromodel are obtained from typical measured characteristics. It is shown that the proposed macromodel can satisfactorily predict both small-signal and large-signal behavior of the op amps.  相似文献   

20.
A new user-oriented I/SUP 2/L macromodel is presented which models I/SUP 2/L performance and predicts operational limits. The macromodel includes n-p-n current gain falloff and injector transport efficiency falloff at both low and high operating currents. Lateral current transfer between adjacent gates may be included in the macromodel. A straightforward parameter measurement scheme is given which requires only simple test gates. The macromodel is easily implemented in commonly available circuit simulators such as SPICE. The modeling of I/SUP 2/L dynamic behavior is demonstrated with computer simulations of a five-stage ring oscillator and `D' flip-flop, where typically 15 percent or better agreement with measured data has been achieved. It is also shown that operational limits of I/SUP 2/L circuits can be accurately predicted. Computer simulation of I/SUP 2/L performance as a function of temperature is discussed. The macromodel is well suited for worst case analysis of I/SUP 2/L, and the close correspondence of the macromodel's parameters to gate geometry makes it possible to use the macromodel to approximately simulate performance changes with layout and geometry variations.  相似文献   

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