一种4路正交时钟校准电路的设计

采用TSMC 40 nm CMOS工艺,设计了一种正交时钟校准电路,它包含2个脉冲宽度调整环路和1个内嵌的延迟锁相环。与其他校准电路相比,本文校准电路无需50%占空比的参考时钟或者单端转差分(STC)电路,就能获得4路占空比为50%的时钟,还能调整时钟的相对相位以输出4路正交时钟。当工作频率为3.125 GHz时,该校准电路能将占空比为10%~90%的输入时钟自动调整至占空比为50%±0.2%的时钟,相位调整范围为58°~122°,电路功耗为2.2 mW,可应用于RapidIO物理层接收机电路中。     

用于CdZnTe探测器的高速前端读出电路

采用0.35 μm CMOS工艺,设计了一种用于CdZnTe探测器的16通道高速前端读出电路。整体电路由16个模拟通道、偏置模块和逻辑控制模块组成,每个通道包括电荷敏感放大器、漏电流补偿电路、成形器、基线保持电路、峰值检测保持电路和时间甄别器。分析了高入射频率下主要电路模块的性能及通道的读出时序。仿真结果表明,本前端读出电路的输入能量范围为29~430 keV@1~15 fC,每个通道功耗小于1.8 mW,等效噪声电荷为87.6e-,最大能补偿的漏电流为50 nA,达峰时间为150 ns,通道增益为50 mV/fC,非线性小于1%,最高注入频率为500 kHz。     

GaAs BFL电路输入输出接口电路的研究

讨论了与ECL兼容的GaAs BFL电路的输入输出接口电路的要求,设计并研究了几种能使GaAs BFL电路与ECL电路相兼容的输入输出接口电路,对它们进行了计算机模拟、投片制作和测试。     

三值电路和电路三要素理论

本文基于四值代数,提出三值电路的统一理论电路三要素(信号,网络和负载)理论,该理论表明:门级与开关级电路间,开关级电路结构间,动态与静态电路间存在简单的转换关系,依照这个关系很容易由三值函数式设计出三值电路,尤其能基于一个电路方程同时推出三值动态和静态电路。     

一种实时自适应前沿消隐电路

基于正激变换器结构,设计了一种实时自适应前沿消隐电路。通过振荡时间消隐和振荡幅度消隐,对最优消隐时间进行追踪,实现实时自适应的前沿消隐,在保证消隐可靠性的基础上降低了系统体积与成本,并确保不限制电路高频化发展。设计的前沿消隐电路能获得消除尖峰振荡的输出电流信息,保证系统能对输出负载变化做出快速响应。基于0.18μm BCD工艺,对电路进行设计。仿真结果表明,该电路在没有其它额外限流功能条件下,启动过冲电压只有50 mV,负载切换时的下掉电压与过冲电压分别为519 mV和578 mV。     

一种新型的双频整流电路

提出一种双频微带整流电路。电路由一个十字型匹配枝节、二极管和直通滤波器组成。匹配枝节实现了二极管在两个频率下同时与50赘匹配,直通滤波器有效抑制了基频和高次谐波。用ADS2011 软件进行分析和设计,10mW 输入功率时,整流电路工作在1. 8GHz 和2. 4GHz 的射频-直流(RF-DC)转换效率分别为75. 8% 和71.1%。实测结果显示,在1. 8GHz 和2. 2GHz 频率上电路有最大RF-DC 转换效率,分别为50%和54%,分析了产生误差的原因。该双频整流电路具有输入功率低、易集成的特点,可用于RFID、嵌入式传感器等电子设备的无线供能。     

三值电路和电路三要素理论

本文基于四值代数,提出三值电路的统一理论－电路三要素（信号,网络和负载）理论,该理论表明,门民开关级电路间,开关级电路结构间,动态与静态电路间存在简单的转换关系,依照这个关系很容易由三值函数式设计出三值电路,尤其能基于一个电路方程同时推出三值动态和静态电路。     

新颖应用电路·实用电路集

在二进制计数器输出端加上适当的译码电路就可构成一个有限状态时序器。用固定频率时钟信号驱动计数器能产生周期相同的输出状态。图中所示电路,是在不同时间间隔产生输出状态的电路。在许多应用场合中用到这种电路。     

电流模电路的通用单元电路

提出了电流模电路中的一个通用积木块－伴随运放。用它能把基于电压运放的电压模电路转换成电流模电路。分析了理想伴随运放的特点和应用,提出一种ＣＭＯＳ伴随运放电路,介绍了用它设计的电流模滤波器。     

验证测试电路的脉冲发生器

验证宽频带测试设备上升时间的限制是件困难的事情。特别是必须知道示波器/探测器组合终端终端的上升时间,以保证测量的完整性。图1就是能提供(上升和下降时间少于250psec的)800psec脉冲的电路。脉冲幅度为10v,电路的源阻抗是50欧姆。除了触发式而不是自激式这一点外,该电路与“参考文献1”中所提到的电路很相似。这种触发特性使它与时钟脉冲或另一个动作同步,可使相应的触发器的输出延迟时间在200psec到5nsec的范围内变化。     

Versatile wideband impedance matching circuit based on current conveyors

The first active impedance matching circuit for RF applications is introduced. It adapts arbitrary output impedances to values between 50 and 250 Omega, from 0 to 5 GHz, and occupies only 0.005 mm² in 0.35 mum SiGe-BiCMOS. It is vastly superior to traditional passive-element solutions by being: the first flexible matching circuit to adapt any impedance to any desired value; the smallest matching circuit ever; and a rare example of wideband matching. Application to a low-noise amplifier proves the potential of the new circuit     

A compact dual-polarized 8.51-GHz rectenna for high-voltage (50 V)actuator applications

This paper describes a dual-polarized rectenna capable of producing a 50-V output voltage that can be used for driving mechanical actuators. This study demonstrates a circuit topology that allows the output of multiple rectenna elements to be combined in order to step up the output voltage. In this paper, an independent rectifying circuit is used for each of two orthogonal polarizations. By proper combination, the output voltage is doubled over that of the single polarization case. Such panels are being explored for use on the next-generation space telescope to eliminate wiring between actuators and provide for true mechanical isolation     

一种数字控制电感测量仪的设计与实现

设计了一个以芯片STM32F407ZGT6为控制核心的数字式电感测量仪,可以对正弦信号源、电感Q值以及电感值实现精确测量。系统硬件电路主要由电源供电电路、信号产生电路、信号调理、测量电路、数据采集与处理以及人机交互等模块组成,其中信号调理电路采用高速运放进行放大和阻抗变换,调节信号幅度的同时保证各级的输入输出阻抗,以达到最高的测量精度。测量电路采用谐振法测量回路谐振频率,然后用伏安法测量可变电容当前值,再通过谐振频率和电容值计算得到被测电感的Q值和电感值。最后经过测试,系统实现了输出范围达50～40MHz 的正弦信号源,测量误差优于0.1%,并且对电感Q值和电感值的测量误差均小于3%。     

11.GHz GaAs Power MESFET Load-Pull Measurements Utilizing a New Method of Determining Tuner Y Parameters

A Ioad-pull technique utilizing a new method of determining tuner Y parameters is proposed for huge-signal characterization of microwave power transistors. Large-signal input-output transfer characteristics of an active circuit containing a GaAs FET and an input matching circuit are measured by inserting a microstrip tuner between the active circuit output drain terminal and the 50-Omega load. The microstrip-tuner Y parameters are determined by comparing the dc bias-dependent small-signal S parameter S/sub 22/ of the active circuit and that of the circuit which contains the active circuit and microstrip tuner. The reflection coefficient presented to the active circuit output drain terminal is derived from tuner Y parameters. Optimal load impedances for output power, obtained with this new Ioad-pull technique, are used to design X-band GaAs FET power amplifiers. An 11-GHz power amplifier with a 3000-mu m gate-width FET chip delivers 1-W microwave power output with 4-dB gain in the 500-MHz band.     

一种小型电容敏感式加速度计的研制

利用弹性良好的铍青铜为材料制作加速度计中的敏感振动元件,研制出电容敏感式加速度计。设计了一种提取差动电容信号的检测电路。给出了电路中所使用的电子元器件,经分析求解得出了电路的输出电压和传感器信号拾取电容变化量之间的正比例关系。经过实验测试,加速度计的灵敏度大约为391.12mV/(m.s-2)。     

高线性满摆幅输入度跨导器及其在gm-C带阻滤波器中的应用

介绍了一种利用MOS管线性区特性实现满摆幅输入的跨导器.通过分析电路中MOS管的二阶效应,利用差分放大器以负反馈形式接入偏置和输出端并联电流源的方法,对电路进行了结构优化,提高了电路的线性度,并降低了输出失调电流.模拟结果表明:跨导器总谐波失真可达到-59.2dB,输出失调电流136nA.用该跨导器组成的gm-C带阻滤波器工作在50Hz的中心频率时,陷波带宽33Hz,陷波深度-39.6dB,可应用于滤除信号中的50Hz市电干扰.     

Evaluating the safety of self-checking circuits

In this paper, we consider the evaluation of the safety of a self-checking circuit with combinational logic. Since the circuit is tested under normal operation, it may stay in different states such as a perfect state in which any erroneous output can be detected, unstable states in which an erroneous output may be detected or may not, a safe-state when the erroneous output has been caught, and a fail-state because the erroneous output is undetected, as time goes on. Consequently, we propose a fail-safe evaluation, using a Markov model to describe the state transitions and predicate the probability of the circuit not being in the fail-state.We include a comparison with existing evaluation methods, the proposed approach being more practical because it estimates the safety of the circuit, which is reducing as time goes on, instead of giving a constant probability measure.This work was supported in part by Research Grant No. 5711 from the Natural Sciences and Engineering Research Council of Canada and by an equipment loan from the Canadian Microelectronics Corporation.     

一种输入输出轨到轨CMOS运算放大器的设计

随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18 μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 mV到电源电压减去50 mV,实现了输入输出轨到轨的目标。     

Modified Wilkinson Power Dividers for Millimeter-Wave Integrated Circuits

A modification of the Wilkinson power divider is presented that eases planar implementation while maintaining performance. By adding transmission lines between the resistor and the quarter-wave transformers of the traditional design, a range of valid solutions exists that meet the conditions of being reciprocal, isolated between the output ports, and matched at all ports. The proposed design is particularly useful at millimeter-wave frequencies where reduced physical dimensions make a circuit configuration suitable for low-cost package-level implementation difficult using traditional methods. Two frequency bands are demonstrated. At V-band, the circuit gives 0.3-dB excess insertion loss, 19-dB isolation, and 50% bandwidth. At the W-band, the circuit gives 0.75-dB excess insertion loss, 24-dB isolation, and 39% bandwidth.     

A single-path pulsewidth control loop with a built-in delay-locked loop

A 1-1.27-GHz single-path pulse width control loop with a built-in delay-locked loop is presented. Based on the proposed circuit, not only can the 50% duty cycle of the output clock be assured but the phase alignment between the reference and output clocks can also be achieved. Moreover, the requirement of the reference clock with 50% duty cycle can be eliminated. By the single-to-complementary circuit and the switched charge pump, the duty cycle error can be reduced. Moreover, the duty cycle of the output clock can be adjusted for applications such as time-interleaved analog-to-digital converters, switched-capacitor circuits, and dc-dc converters. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS process. The power consumption is 150 mW and the die area of the core circuit is 0.47/spl times/0.3 mm/sup 2/. The duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.