Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC (analog-to-digital converter) for wireless local area network standards is presented. A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted; however, this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR (signal to noise and distortion ratio), using 4-bit ADCs in both stages to minimize the quantization noise. Data weighted averaging technology is therefore used to decrease the mismatch noise induced by the 4-bit DACs, which improves the SFDR (spurious free dynamic range) of the ADC.The modulator has been implemented by a 0.18μm CMOS process and operates at a single 1.8 V supply voltage.Experimental results show that for a 1.25 MHz @ -6 dBFS input signal at 160 MHz sampling frequency, the improved ADC with all non-idealities considered achieves a peak SNDR of 80.9 dB and an SFDR of 87 dB, and the effective number of bits is 13.15 bits.     

A third-order Δ-Σ modulator using second-ordernoise-shaping dynamic element matching

A multibit Δ-Σ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit Δ-Σ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a Δ-Σ ADC and DAC using the second-order NSDEM method. The test chip of the third-order Δ-Σ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC(analog-to-digital converter) for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted;however,this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR(signal to noise and distortion ratio),using 4-bit ADCs in both stages to minimize the quantization noise.Data weighted ...     

A 2.5-V sigma-delta modulator for broadband communicationsapplications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

A 14-bit current-mode ΣΔ DAC based upon rotated dataweighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order ΣΔ digital-to-analog converter (DAC) with 64× oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The ΣΔ DAC is fabricated in a 2-μm CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA     

A wideband cascaded sigma-delta modulator with improved nonlinearity effects

This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the nonlinearity effects of components. This architecture offers a new noise-shaping function to achieve high resolution in wideband applications and reduce digital-analogue converter (DAC) mismatch from the multi-bit feedback. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effectively reduce the non-ideal effects such as DAC mismatch. The mismatches between the two stages, such as in the gain error and pole error, may seriously degrade performance. The blind on-line calibration technique is used to eliminate these imperfect analogue circuit errors in the digital circuit. Accordingly, this architecture can reduce the over sampling ratio (OSR), and the in-band noise can be significantly suppressed to achieve a high resolution in Matlab and Switcap2 simulations. Simulation results indicate this sigma-delta modulator is very efficient in wide bandwidth applications.     

A 2nd-order sigma-delta mismatch-shaping current-steering DAC for zigbee transmitters

A low-power mismatch-tolerant current-steering digital-to-analog converter (DAC) was presented in this paper for ZigBee transmitter applications. Mismatches among the current units induce harmonic distortions and random analog noise which severely limit the linearity and resolution of the converter. 1^st-order and 2^nd-order sigma-delta dynamic element matching (DEM) schemes and the corresponding elements selection patterns were introduced in this paper, and the later was then applied to the DAC to spectrally shape the mismatches of the DAC without adding complex digital hardware. Measurement results showed that the proposed 2^nd-order DEM improved the resolution of the DAC from 4.5-bit to 11.4-bit, DNL from a maximum of 0.6 to 0.04LSB and INL from 1.1 to 0.07LSB. The SFDR, SNR and ENOB were respectively 70 dB, 58 dB and 7.3-bit for a 50 kHz@-6dBFS input signal.     

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibitdelta-sigma modulation at 8× oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8× oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm² chip in 0.5-μm CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation     

Design considerations of calibration DAC in self-calibrated SAR A/D converters

A capacitive calibration digital-to-analog converter (CDAC) is commonly used to reduce the mismatch-induced linearity errors for successive approximation register (SAR) analog-to-digital converters (ADC) employing capacitor arrays. There are complicated design considerations in determining the number of bits, the unit capacitor value and even the parasitic capacitors of the CDAC, as these factors affect or are determined by the achievable ADC resolution, the main DAC's capacitance, and the main DAC unit capacitance value, etc. This paper is the first to present a systematic analysis on these relationships. The analysis is validated by behavioral and circuit simulation results.     

A low-power multi-bit /spl Sigma//spl Delta/ modulator in 90-nm digital CMOS without DEM

Multi-bit sigma-delta modulators are widely used in analog-to-digital conversion especially in the modern deep-submicron CMOS process. As the quantizer resolution of /spl Sigma//spl Delta/ modulators increases, the SNR performance improves. However, the feedback DAC has to maintain high linearity. The general practice to achieve that is to use dynamic element matching (DEM). The methodology proposed in this paper will greatly reduce the complexity or even avoid usage of DEM for multi-bit /spl Sigma//spl Delta/ modulators. The proposed methodology-truncation error shaping and cancellation-reduces the feedback DAC levels for multi-bit quantizers. A prototype was designed in a standard CMOS 90-nm process to demonstrate the proposed methodologies. It achieved targeted performance without DEM at low power consumption with small silicon area.     

A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC.     

A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

In this paper, an ultra-low-power successive approximation register analog-to-digital converter (ADC) for energy limited applications is presented. The ADC resolution is enhanced by using a noise-shaping technique which does not need any integrator and only uses a finite impulse response (FIR) filter. To provide a first-order noise-shaping, the quantization error is firstly extracted by using the digital-to-analog converter (DAC) dummy capacitor and it is then employed in the error feedback scheme. The proposed structure employs a low-gain and low-swing operational transconductance amplifier (OTA) to realize the FIR filter which operates only at the sampling phase. To minimize the power consumption of the ADC analog part, the OTA is powered off during the conversion phase. The proposed ADC is designed and simulated in a 90 nm CMOS technology using Spectre with a 0.5 V single power supply. The simulated ADC uses a fully-differential 8-bit charge redistribution DAC with an oversampling ratio of 8 and achieves 10.7-bit accuracy. The simulated average power consumption is 4.53 μW and the achieved maximum SNDR and SFDR are 66.1 and 73.1 dB, respectively, resulting in a figure of merit of 27.6 fJ/conversion-step.     

A novel noise efficient feedback DAC within a switched capacitor /spl Sigma//spl Delta/ ADC

Efficient sampling of the reference noise within a bilinear switched capacitor /spl Sigma//spl Delta/ analog-to-digital converter (ADC), resulting in improved thermal noise performance is presented. Bilinear integrators contain a zero at the Nyquist frequency, with the result that no charge is transferred from the reference when a transition occurs in the modulator output. The average noise power added by the reference digital-to-analog converter (DAC) can be reduced substantially if the reference DAC is sampled only when charge is to be transferred. For midscale inputs, the sampled noise from a single bit reference DAC is reduced by more than 5 dB. When multibit quantization and feedback is used the reference noise can be further suppressed, in the case of 5 bits of feedback the reference noise is reduced by more than 20 dB.     

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signalbandwidth and 89 dB SNR

A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-μm CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal     

A multibit sigma-delta ADC for multimode receivers

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-/spl mu/m CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator, thereby enabling the use of the highest resolution quantizer yet reported in a multibit sigma-delta analog-to-digital converter of this speed. The part achieves 95-dB peak spurious-free dynamic range and 77-dB signal-to-noise ratio over a 625-kHz bandwidth, and consumes 30 mW at a sampling frequency of 23 MHz. The part achieves 70-dB signal-to-noise ratio over a 1.92-MHz bandwidth and dissipates 50 mW when clocked at 46 MHz.     

一种低功耗结构的ADC设计

逐次逼近结构ADC是中速中高分辨率应用中的常见结构,其中DAC多采用电容阵列结构,但其动态功耗随分辨率的增加而增加.论文设计了一种新颖的10位ADC结构,它采用两级进行模数转换的方法,高位采用低功耗的并行模数转换结构,低位采用逐次逼近模数转换结构,通过合理设计高低位转换位数、低功耗比较器,采用简单的二进制搜索算法,有效...     

Continuous time sigma-delta modulator based on binary weighted charge balance

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz