High-voltage (3 kV) UMOSFETs in 4H-SiC

Vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) in 4H-SiC having both trench oxide protection and junction termination extension (JTE) are reported for the first time. Devices are fabricated with and without counter-doped channels. Blocking voltages and specific on-resistances are 3360 V and 199 mΩ-cm² for doped-channel FETs and 3055 V and 121 mΩ-cm² for FETs without doped channels. These blocking voltages are the highest reported to date for UMOSFETs in SiC     

2.6 kV 4H-SiC lateral DMOSFETs

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET     

4H-SiC RF power MOSFETs

A 4H silicon carbide lateral RF MOSFET has been fabricated and characterized for the first time. The improved performance of this device was facilitated by a two-metal-layer process, which optimizes the conflicting requirements of acceptable inversion-layer mobility and low contact resistance. The cut-off frequency of the device with 1-μm gate length was in excess of 7 GHz     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

Development of 17 kV 4H-SiC PiN diode

The design, fabrication, and electrical characteristics of a 4H-SiC PiN diode with breakdown voltage higher than 17 kV are presented. The three-zone JTE has been used in the fabrication. Numerical simulations have been performed to optimize the parameters of the edge termination technique. The epilayer properties of the N-type are 175 μm with a doping of 2×10¹⁴cm^-3. With the three-zone JTE, a typical breakdown voltage of 17 kV has been achieved.     

6.5kV,25 A 4H-SiC功率DMOSFET器件

<正>与硅IGBT相比,SiC高压功率DMOSFET器件的导通电阻和开关损耗更低,工作温度更高,在智能电网的应用中具有巨大的应用前景。南京电子器件研究所研制出一款6.5kV25ASiC功率DMOSFET器件。建立了高压SiC DMOSFET仿真模型并开展元胞结构设计,通过采用低界面态密度栅极氧化层制备以及JFET区选择掺杂等先进工艺技术,在60μm厚外延层上制备了6.5 kV SiC DMOSFET,芯片有源区尺寸37 mm~2。该器件击穿电压大于6.9 kV,导通电流大于25 A,峰值有效沟道迁移率为23 cm~2/(V·s),比导通电阻降低到44.3 mΩ·cm~2,缩小了与国际先进水平的差距。     

6.5kV,5A4H-SiC功率DMOSFET器件

报道了在60μm厚、掺杂浓度1.3×10~(15) cm~(-3)的外延层上制备4H-SiC功率DMOSFET器件的研究结果。器件击穿电压大于6.5 kV,导通电流大于5 A,相对于之前的报道结果,器件导通能力提升了25倍。器件采用由55根环组成的,450μm宽的浮空场限环作为器件终端结构。通过1 250°C热氧化工艺和NO退火技术,完成器件栅介质层制备。通过横向MOSFET测试图形,提取器件峰值有效沟道迁移率为23 cm~2/(V·s)。器件有源区面积为0.09 cm~2,在栅极电压20 V、室温下,器件比导通电阻为50 mΩ·cm~2。在漏极电压6.5 kV时,器件漏电流为6.0μA,对应器件漏电流密度为30μA·cm~(-2)。基于此设计结构,通过设计实验,提取了SiC DMOSFET器件中电阻比例组成。     

基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

本文对比了NO退火和磷掺杂两种栅钝化工艺,其中磷钝化采用了平面扩散源进行掺杂,通过C-V特性进行了4H-SiC/SiO₂界面特性评价,使用Terman法分析计算获得距导带底0.2-0.4eV范围内界面态密度.结果表明引入磷比氮能更有效降低界面态密度,提高沟道载流子迁移率.其次,对比了两种栅钝化工艺制备的4H-SiC DMOSFET器件性能,实验表明采用磷钝化工艺处理的器件性能更优.最后,基于磷掺杂钝化工艺首次制备出击穿电压为1200V、导通电阻为20mΩ、漏源电流为75 A、阈值电压为2.4V的4H-SiC DMOSFET.     

10 A, 2.4 kV Power DiMOSFETs in 4H-SiC

We report the characteristics of large area (3.3 × 3.3 mm ²) high-voltage 4H-SiC DiMOSFETs. The MOSFETs show a peak MOS channel mobility of 22 cm²/V·s and a threshold voltage of 8.5 V at room temperature. The DiMOSFETs exhibit an on-resistance of 4.2 mΩ·cm² at room temperature and 85 mΩ·cm² at 200°C. Stable avalanche characteristics at approximately 2.4 kV are observed. An on-current of 10 A is measured on a 0.103 cm² device. High switching speed is also demonstrated. This suggests that the devices are capable of high-voltage, high-frequency, low-loss switching applications     

3300V 4H-SiC MOSFET 设计与加工

成功设计并制造了击穿电压超过3300V 的4H-SiC MOSFET。通过数字仿真优化了漂移层和DMOSFET有源区参数。漂移层N型外延厚度为33微米并且掺杂浓度为2.5E15cm-3。器件采用浮空场限制环作为终端。当栅极电压为20V,漏极电压为2.5V时,漏极电流为5A。     

I-V characteristics of high-voltage 4H-SiC diodes with a 1.1-eV Schottky barrier

The I-V characteristics of high-voltage 4H-SiC diodes with a Schottky barrier ∼1.1 eV in height are measured and analyzed. The forward I-V characteristics proved to be close to “ideal” in the temperature range of 295–470 K. The reverse I-V characteristics are adequately described by the model of thermionic emission at the voltages to 2 kV in the temperature range of 361–470 K if, additionally, a barrier lowering with an increase in the band bending in the semiconductor is taken into account.     

4H-SiC power devices for use in power electronic motor control

Silicon carbide (SiC) is an emerging semiconductor material which has been widely predicted to be superior to both Si and GaAs in the area of power electronic switching devices. This paper presents an overview of SiC power devices and concludes that the MOS turn-off thyristor (MTO™), comprising of a hybrid connection of SiC gate turn-off thyristor (GTO) and MOSFET, is one of the most promising near term SiC switching device given its high power potential, ease of turn-off, 500°C operation and resulting reduction in cooling requirements. The use of a SiC and an anti-parallel diode are primary active components which can then be used to construct an inverter module for high-temperature, high-power direct current (d.c.) motor control.     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

采用浮空场限制环的耐压10kV碳化硅二极管的开发

The design, fabrication, and electrical characteristics of the 4H-SiC JBS diode with a breakdown voltage higher than 10 kV are presented. 60 floating guard rings have been used in the fabrication. Numerical simulations have been performed to select the doping level and thickness of the drift layer and the effectiveness of the edge termination technique. The n-type epilayer is 100 μm in thickness with a doping of 6 × 10^14 cm^-3. The on-state voltage was 2.7 V at JF = 13 A/cm^2.     

3.3 kV 4H-SiC DMOSFET with a source-contacted dummy gate for high-frequency applications

In this paper,a 4H-SiC DMOSFET with a source-contacted dummy gate(DG-MOSFET)is proposed and analyzed through Sentaurus TCAD and PSIM simulations.The source-contacted MOS structure forms fewer depletion regions than the PN junction.Therefore,the overlapping region between the gate and the drain can be significantly reduced while limiting RON degradation.As a result,the DG-MOSFET offers an improved high-frequency figure of merit(HF-FOM)over the conventional DMOSFET(C-MOSFET)and central-implant MOSFET(CI-MOSFET).The HF-FOM(RON×QGD)of the DG-MOSFET was improved by 59.2％and 22.2％compared with those of the C-MOSFET and CI-MOSFET,respectively.In a double-pulse test,the DG-MOSFET could save total power losses of 53.4％and 5.51％,respectively.Moreover,in a power circuit simulation,the switching power loss was reduced by 61.9％and 12.7％in a buck converter and 61％and 9.6％in a boost converter.     

Optimized design of 4H-SiC floating junction power Schottky barrier diodes

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics.Compared with the conventional power Schottky barrier diode,the device structure is featured by a highly doped drift region and embedded floating junction region,which can ensure high breakdown voltage while keeping lower specific on-state resistance,solved the contradiction between forward voltage drop and breakdown voltage.The simulation results show that with optimized structure parameter,the breakdown voltage Can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

浮结型碳化硅肖特基势垒功率二极管的优化设计

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics. Compared with the conventional power Schottky barrier diode, the device structure is featured by a highly doped drift region and embedded floating junction region, which can ensure high breakdown voltage while keeping lower specific on-state resistance, solved the contradiction between forward voltage drop and breakdown voltage. The simulation results show that with opti- mized structure parameter, the breakdown voltage can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

基于一种可靠非均匀场限环终端结构的1.4kV 4H型碳化硅PiN二极管

This paper presents the design and fabrication of an effective, robust and process-tolerant floating guard ring termination on high voltage 4H-SiC PiN diodes. Different design factors were studied by numerical simulations and evaluated by device fabrication and measurement. The device fabrication was based on a 12 μm thick drift layer with an N-type doping concentration of 8 × 10^15 cm^-3. P^＋ regions in the termination structure and anode layer were formed by multiple aluminum implantations. The fabricated devices present a highest breakdown voltage of 1.4 kV, which is higher than the simulated value. For the fabricated 15 diodes in one chip, all of them exceeded the breakdown voltage of 1 kV and six of them reached the desired breakdown value of 1.2 kV.