A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.     

DSA 4K static RAM

A high-performance diffusion self-aligned (DSA) 4K static RAM, which operates on a single power supply of 5 V without any clock input, has been fabricated. The RAM, composed of DSA MOSTs, depletion MOSTs, and high-impedance polysilicon load resistors, was designed using nonclocked static circuit techniques. The memory cell size and the chip size are 45/spl times/40 /spl mu/m and 3.88/spl times/3.45 mm, respectively. A typical access and cycle time of 76 ns is realized at a power dissipation of 500 mW. The RAM can retain data in a standby mode with a reduced supply voltage of 1.5 V, thereby decreasing the power dissipation to 60 mW. The active power dissipation can be decreased in a RAM fabricated with a lower ion-implantation dose to the depletion load MOSTs; thus the RAM may also be useful for memory applications where low power dissipation is of primary importance.     

A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture

A 1-Mb dynamic RAM has been fabricated using 1.2-/spl mu/m double-level metal CMOS technology. A novel divided bitline matrix architecture allows the conventional double-polysilicon planar memory cell to be used without sacrificing signal-to-noise (S/N) ratio or die efficiency. Optimized for high bandwidth, the device uses static column circuitry and a 256K/spl times/4 organization to achieve data rates >180 Mb/s at worst-case voltage and temperature conditions. The 5.97-mm/spl times/11.4-mm die incorporates a flexible laser blown fuse link redundancy scheme which can repair a wide variety of fabrication defects. Typical row access and cycle times are 85 and 190 ns, respectively, achieving >21-Mb/s bandwidth in the non-optimized row access mode. Although some DC power is dissipated in static circuitry, active power consumption has been kept to 225 mW (45 mA), and standby power consumption has been reduced to 2.5 mW (0.5 mA).     

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-μm CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems     

A scarce-state-transition Viterbi-decoder VLSI for bit error correction

A high-speed Viterbi decoder VLSI with coding rate R=1/2 and constraint length K=7 for bit-error correction has been developed using 1.5-/spl mu/m n-well CMOS technology. To reduce both hardware size and power dissipation, a recently developed scarce-state-transition (SST) Viterbi decoding scheme has been utilized. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42 K gates have been integrated on a chip with a die size of 9.52/spl times/10.0 mm/SUP 2/. The VLSI decoder has achieved a maximum data throughput rate of 23 Mb/s with a net coding gain of 4.4 dB (at 10/SUP -4/ bit-error rate). The chip dissipates only 825 mW at a data rate of 10 Mb/s.     

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

8192-bit block addressable CCD memory

Design data and experimental characteristics are given on an 8192-bit n-channel charge-coupled memory device, intended for applications requiring shorter latency than ordinary MOS shift registers or fixed-head disks and at potentially lower cost than either MOS shift registers or random-access memories. This was achieved by dividing the array into 32 memory blocks of 256 bits each, with addressable, random access to any block, permitting average latency of approximately 100 /spl mu/s. A two-level overlapping polysilicon gate process was used, with conservative design tolerances. Power dissipation on-chip, plus capacitive drive power during data access at 1 MHz is approximately 250 mW, and less than 5 mW during standby at 20 kHz with data retention.     

Design of a high-performance 1024-B switched capacitor p-channel IGFET memory chip

IGFET switched-capacitor memory cells are incorporated into a fully decoded dynamic, 1024-word by 1-b p-channel random-access memory. With 10-V drive circuitry, chip access time is measured to be 150 ns and cycle time is 300 ns. Measured on-chip power dissipation at a 300 ns cycle was less than 80 mW (80 /spl mu/W/b) and is correspondingly lower at lower speeds. Refresh power at 100/spl deg/C is less than 1 /spl mu/W/b.     

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

A 200-mW GaAs 1 K SRAM with 2-ns cycle time

A very high-speed and low-power 1024/spl times/1 SRAM has been designed and fabricated using a normally-off recessed-gate FET technology. Minimum gate length is 0.7 /spl mu/m. A minimum access time of 1.4 ns has been obtained with a power dissipation of 210 mW. The memory cell area is 1197 /spl mu/m/SUP 2/ and the chip size is 1.91/spl times/2.21 mm/SUP 2/. The output voltage swing across a 50-/spl Omega/ load is 700 mV. The maximum simulated yield for 1 K SRAMs is discussed theoretically. A mean standard deviation in threshold voltage less than 15 mV is required to obtain 100% design yield. The SRAM has been shown to be fully operational using the march and checkerboard tests and exhibits read and write cycle times of 2 ns.     

A high-speed 16-kbit n-MOS random-access memory

This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.     

Level selection based pre-emphasis for PAM transmitter

A novel pre-emphasis for a multi-level PAM transmitter is presented. Overshooting and power consumption are reduced through a level selection approach. The test chip fabricated using a TSMC 0.18 /spl mu/m CMOS process shows 142 mW power dissipation with 500 Mbit/s symbol rate and 1 Gbit/s equivalent data rate.     

A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture

A still-image encoder based on vector quantization (VQ) has been developed using 0.35-/spl mu/m triple-metal CMOS technology for encoding a high-resolution still image. The chip employs the needless calculation elimination method and the adaptive resolution VQ (AR-VQ) technique. The needless calculation elimination method can reduce computational cost of VQ encoding to 40% or less of the full-search VQ encoding, while maintaining the accuracy of full-search VQ. AR-VQ realizes a compression ratio of over 1/200 while maintaining image quality. The processor can compress a still image of 1600/spl times/2400 pixels within 1 s and operates at 66 MHz with power dissipation of 660 mW under 2.5-V power supply, which is 1000 times larger performance per unit power dissipation than the software implementation on current PCs.     

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time

An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time, 900 mW power dissipation, and a chip size of 18.3 mm/SUP 2/ has been developed for caches and control memories of high-performance computer systems. The 1K/spl times/4 organisation mode combines the lower cost per bit of a 4K-bit device with the higher memory-module design flexibility of a 1K word unit. The excellent speed performance together with the high packing density have been achieved by using an oxide isolation technology with oxide-walled emitters in conjunction with novel circuit techniques.     

A 4096-B one-transistor per bit random-access memory with internal timing and low dissipation

Some details of a 4096-b p-channel random-access memory with a one-transistor per bit cell are discussed. The main features of the design are the sensitive sense-refresh amplifier, allowing a storage capacitance of only 0.065 pF, application of the bootstrap principle to obtain an access time of 400 ns, a power dissipation of 150 mW, and the implementation of a new, fast shift register as an internal timing circuit. This timing circuit generates the memory clock signals, reducing the number of external clock signals to one clock and a chip select signal. The chip size is 3.01/spl times/4.44 mm/SUP 2/.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

On the analysis and design of CMOS-bipolar SRAMs

The design and operation of a CMO-bipolar SRAM cell, which incorporates cross-coupled CMOS and n-p-n access transistors, is discussed. A column circuitry to accompany this cell is proposed. Simulation results attributing column access time, standby power dissipation, and active power dissipation of 6-8 ns, 6.5 nW/bit, and 4 mW/b, respectively, for a cell area of ~450 /spl mu/m/SUP 2/, suggest the suitability of this approach for applications requiring density, performance, and moderate power.     

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.