共面波导馈电的超宽带天线研究

设计了一种共面波导馈电的超宽带(UWB)天线,其阻抗带宽达到341%。所设计的天线印刷在尺寸为28mm×21mm×1.6mm,介电常数为2.65的聚四氟乙烯介质基板上。同时为了实现该天线与WLAN(5.725~5.825GHz)系统的协同工作,本文在共面波导的地面上刻蚀一个矩形槽,实现UWB与WLAN系统的兼容。利用高频结构仿真软件HFSS对影响天线性能的主要物理参数进行仿真、分析和优化,得到天线的优化尺寸。实验结果表明,该天线比传统微带贴片天线性能有了较大的提高,从而表明了利用共面波导馈电和刻蚀矩形槽的天线设计方法实现多种宽带通信系统兼容的可行性和有效性。     

一种新颖的单绕组自驱动同步整流方案的研究

对低压／大电流输出DC／DC变换器，提出了一种新颖的单绕组自驱动同步整流(SR)方案。该方案无需复杂的逻辑控制电路，即能实现同步整流管的自驱动。与传统自驱动方案相比，该方案解决了主变绕组电压为零时段副边同步整流管不能同时导通的问题，拓宽了自驱动同步整流的应用拓扑范围，特别适用于变压器对称工作的低压／大电流输出DC／DC变换器。基于该方案制作的2．5V输出对称半桥变换器原理样机验征了分析和设计的正确性。     

基于边界消耗暂态谐波能量的柔性直流输电线路保护新方案

超导型故障限流器在柔性直流输电工程中能有效地限制故障电流的峰值和陡度,类比于传统高压直流输电系统的物理边界。将超导型故障限流器看作是柔性直流输电系统的边界,提出了一种基于边界消耗暂态谐波能量的柔性直流线路保护方案。该保护方案利用正极或负极线路整流侧边界消耗的暂态谐波能量启动保护,利用两极线路的整流侧和逆变侧边界消耗的暂态谐波能量差辨别区内外故障,利用正、负极线路整流侧边界消耗的暂态谐波能量之比进行故障选极。理论分析和仿真结果表明,该保护方案适用于各种工况,几乎不受过渡电阻和故障位置的影响,且对采样率要求低,具有重要的工程应用价值。     

A novel control scheme for DFIG-based wind energy systems under unbalanced grid conditions

This paper presents an analysis and a novel control scheme for a doubly fed induction generator (DFIG) based wind energy generation under unbalanced grid voltage conditions. The control objectives are: (i) to limit the rotor currents, (ii) to suppress ripples in the torque and (iii) to suppress the dc-link voltage fluctuation through converter controls. Negative sequence compensation techniques by one of the converters, namely, the rotor side converter (RSC) or the grid side converter (GSC) in a DFIG are discussed and their limitations are presented. A coordinated control scheme with a concise structure compared to the conventional dual sequence control structure is proposed in this paper. The RSC is controlled to suppress ripples in the torque and the rotor currents while the GSC is controlled to suppress ripples in the dc-link voltage by considering the rotor power effect. The major contributions of the paper include: (i) the presentation of the limitation of negative sequence compensation using one converter; (ii) development of a concise coordination control scheme which is free of low pass filters and uses a reduced number of reference frame transformation. Matlab/Simulink tests for a 2MW DFIG demonstrate the effectiveness of the control scheme.     

A novel hybrid PSO-PS optimized fuzzy PI controller for AGC in multi area interconnected power systems

In this paper, a novel hybrid Particle Swarm Optimization (PSO) and Pattern Search (PS) optimized fuzzy PI controller is proposed for Automatic Generation Control (AGC) of multi area power systems. Initially a two area non-reheat thermal system is used and the gains of the fuzzy PI controller are optimized employing a hybrid PSO and PS (hPSO-PS) optimization technique. The superiority of the proposed fuzzy PI controller has been shown by comparing the results with Bacteria Foraging Optimization Algorithm (BFOA), Genetic Algorithm (GA), conventional Ziegler Nichols (ZN), Differential Evolution (DE) and hybrid BFOA and PSO based PI controllers for the same interconnected power system. Additionally, the proposed approach is further extended to multi source multi area hydro thermal power system with/without HVDC link. The superiority of the proposed approach is shown by comparing the results with some recently published approaches such as ZN tuned PI, Variable Structure System (VSS) based ZN tuned PI, GA tuned PI, VSS based GA tuned PI, Fuzzy Gain Scheduling (FGS) and VSS based FGS for the identical power systems. Further, sensitivity analysis is carried out which demonstrates the ability of the proposed approach to wide changes in system parameters, size and position of step load perturbation The proposed approach is also extended to a non-linear power system model by considering the effect of governor dead band non-linearity and the superiority of the proposed approach is shown by comparing the results of hybrid BFO-PSO and craziness based PSO approach for the identical interconnected power system. Finally, the study is extended to a three area system considering both thermal and hydro units with different controllers in each area and the results are compared with hybrid BFO-PSO and ANFIS approaches.     

A novel active auxiliary circuit for efficiency enhancement integrated with synchronous buck converter

In this paper, a novel auxiliary circuit is introduced for the synchronous buck converter. This auxiliary circuit provides zero‐current, zero‐voltage switching conditions for the main and synchronous switches while providing zero‐current condition for the auxiliary switch and diodes. The proposed active auxiliary circuit integrated with synchronous buck converter that emanates to zero‐voltage transition (ZVT)–zero‐current transition (ZCT) pulse width‐modulated (PWM) synchronous buck converter is analyzed, and its operating modes are presented. The additional voltage and current stresses on main, synchronous and auxiliary switches get decimated because of the resonance of the auxiliary circuit that acts for a small segment of time in the proposed converter. The important design feature of soft‐switching converters is the placement of resonant components that mollifies the switching and conduction losses. With the advent of ZVT–ZCT switching, there is an increase in the switching frequency that declines the resonant component values in the converters and also constricts the switching losses. The characteristics of the proposed converter are verified with the simulation in the Power Sim (PSIM) software co‐simulated with MATLAB/SIMULINK environment and implemented experimentally. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel PDWC‐UCO algorithm‐based buffer placement in FPGA architecture

Clock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high‐performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)‐Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC‐UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip‐Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd.     

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs

A high SNDR discrete-time (DT) 2-1 MASH sigma-delta modulator (SDM) for 15-MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five-bit flash quantizer was adopted in both stages to improve the overall signal-to-noise and distortion ratio (SNDR) performance, and third-order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18-μm CMOS technology, the occupied area of the modulator was 0.24 mm² and dissipation power 25.4 mW from a 1.8-V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15-MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious-free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5-dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15-MHz bandwidth. A 15-MHz bandwidth multibit MASH2-1 discrete-time sigma-delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High-order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18-μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15-MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high-frequency biomedical imaging or sensing systems, and so on.     

A novel modulation technique with interleaved‐and‐shifted shoot‐through state placement for quasi‐Z‐source inverters

In this paper, a single‐phase quasi‐Z‐source (qZS) inverter (qZSI), integrating the pulse width modulation (PWM) control with interleaved‐and‐shifted shoot‐through state (STS) placement modulation technique, is proposed to simultaneously achieve both dc voltage boost and dc‐ac inversion. Instead of placing the STS in both inverter legs simultaneously, the addressed method inserts the STS only in left/right inverter leg separately during the positive/negative half cycle of the output voltage to reduce switching losses and thermal stresses of the power devices. The STS shift is also studied to decrease the switching numbers of power devices and thus can improve the efficiency further. Theoretical analysis and design guidelines of the studied inverter are included. Improvement in effectiveness and performance of the devised scheme and modulation strategy are proved experimentally and compared with the previous studies on a built laboratory prototype.     

基于广义短路比的多馈入直流系统受端电网结构优化方法

大规模直流多点馈入导致受端交流系统电压支撑能力相对变弱,电压稳定问题突出。因此亟须提升受端交流系统强度,但这在加强交流系统电气联系的同时也加剧了短路电流水平。受端交流系统的结构同时影响系统强度和短路电流水平,优化系统结构有助于协调系统强度与短路电流水平之间的矛盾。基于广义短路比的灵敏度分析和支路追加法,文中提出了一种电网结构优化方法。首先,分析了广义短路比和短路电流水平之间的变化关系;其次,研究了交流系统结构调整对上述2项指标的影响,分析了协调2项指标后的系统结构调整综合效益;最后,对不同直流落点进行分类,给出相应的受端交流系统结构优化调整策略。仿真算例验证了所提策略的可行性和有效性。     

A finite frequency approach to filter design for uncertain discrete‐time systems

This paper studies the problem of finite frequency filter design for linear time‐invariant discrete‐time systems with polytopic uncertainties. Generalized Kalman–Yakubovich–Popov lemma is exploited to formulate the filter design problem in finite frequency domain. A design method is presented in terms of solutions to a set of linear matrix inequalities. A numerical example is given to illustrate the effectiveness of the proposed method. Copyright © 2007 John Wiley & Sons, Ltd.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.