A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.      

Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

Innovative Voltage Driving Pixel Circuit Using Organic Thin-Film Transistor for AMOLEDs

In this work, we propose a novel active-matrix organic light-emitting diode displays (AMOLED) pixel circuit based on organic thin-film transistor (OTFT) architecture, which consisted of four switches, one driving transistor, and a capacitor. The pentacene-based OTFT device possesses a field-effect mobility of 0.1 ${hbox{cm}}^{2} /{hbox{V}}cdot{hbox{s}}$, a threshold voltage of $-{hbox{1.5}}~{hbox{V}}$ , subthreshold slope of 1.8 V/decade and an on/off current ratio ${hbox{10}} ^{6}$. The resultant voltage-driving pixel circuit, named “Complementary Voltage-Induced Coupling Driving” (CVICD), is different from the current-driving scheme and can appropriately operate at low gray level for the low-mobility OTFT circuitry. The current non-uniformity less than 2.9% is achieved for data voltage ranging from 1 to 17 V by SPICE simulation work. In addition, the new external driving method can effectively reduce the complexity of OLED pixel circuitry.      

Active Matrix OTFT Display With Anodized Gate Dielectric

A complete process for an active-matrix (AM) organic thin-film transistor (OTFT) polymer dispersed liquid crystal (PDLC) display is presented. Evaporated pentacene is used as semiconductor. The display comprises 64$times$64 pixel, each with a pixel pitch of $({hbox{312.5}} times {hbox{312.5}}) mu{hbox{m}}^2$. The AM display is fabricated with standard photolithographic processes. Since all process temperatures are below 180$^{circ}$C the processes for the AM backplane can be easily transferred to plastic substrates like PEN or PET. Due to the thin anodically oxidized ${hbox{Al}}_2$ ${hbox{O}}_3$ gate dielectric with a thickness of 60 nm and $varepsilon_{rm r}=9$, driving voltages between 10 and 12 V are sufficient. To protect the pentacene against the PDLC, it is encapsulated with sputtered ${hbox{Ta}}_2 {hbox{O}}_5$ layer. After the passivation a field effect mobility of 0.2 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ is obtained for the OTFTs.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

A Compact Four-Wavelength Quantum-Cascade Laser Source

A four-wavelength quantum-cascade (QC) laser source that operates using a single current channel is presented. The source includes two different heterogeneous cascade QC lasers, one with emission wavelengths of 7.0 $mu{hbox {m}}$ and 11.2 $mu{hbox {m}}$, and the other with 8.7 $mu{hbox {m}}$ and 12.0 $mu{hbox {m}}$ . For 3.0-mm and 3.5-mm cavity lengths, QC lasers with emission wavelengths of 8.7, 11.2, and 12.0 $mu{hbox {m}}$ have threshold current densities within less than a factor of 2, which allows them to be conveniently driven in series by a single current source.      

Low-Threshold Strained Quantum-Well GaSb-Based Lasers Emitting in the 2.5- to 2.7-$mu$ m Wavelength Range

GaInAsSb–GaSb strained quantum-well (QW) ridge waveguide diode lasers emitting in the wavelength range from 2.51 to 2.72 $ mu{hbox {m}}$ have been grown by molecular beam epitaxy. The devices show ultralow threshold current densities of 44 $hbox{A}/{hbox {cm}}^{2}$ (${L}rightarrow infty $) for a single QW device at 2.51 $ mu{hbox {m}}$, which is the lowest reported value in continuous-wave operation near room temperature (15 $^{circ}hbox{C}$) at this wavelength. The devices have an internal loss of 3 ${hbox {cm}}^{-1}$ and a characteristic temperature of 42 K. By using broader QWs, wavelengths up to 2.72 $mu{hbox {m}}$ could be achieved.      

A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly

A fully-integrated 60-GHz transceiver system with on-board antenna assembly is presented. Incorporating on-off keying (OOK) and low-cost antenna designs, this prototype demonstrates a low-power solution for multi-Gb/s wireless communication. The enhanced OOK modulator/demodulator obviates baseband and interface circuitry, revealing a compact solution. Two antenna structures, folded dipole and patch array, are employed to fully examine the performance. Designed and fabricated in 90-nm CMOS technology, the transmitter and the receiver consume 183 and 103 mW and occupy 0.43 and 0.68 ${hbox {mm}}^{2}$, respectively. With 4 $times$ 3 patch antenna array, the transceiver achieves error-free operation $({hbox{BER}}<10^{-12})$ for $2^{31}-1$ PRBS of 1 Gb/s over a distance of 60 cm.      

Experimental Demonstration of Deeply-Etched SiO$_{2}$ Ridge Optical Waveguides and Devices

Deeply-etched ${hbox{SiO}}_{2}$ optical ridge waveguides are fabricated and characterized. A detailed discussion of the fabrication process (especially for the deep etching process) is presented. The measured propagation losses for the fabricated waveguides with different core widths range from $0.33sim {hbox {0.81}}~{hbox {dB}}/{hbox {mm}}$. The loss is mainly caused by the scattering due to the sidewall roughness. The losses in bending sections are also characterized, which show the possibility of realizing a small bending radius (several tens of microns). 1 $,times {rm N}$ ( ${rm N}=2$, 4, 8) multimode interference couplers based on the deeply-etched ${hbox{SiO}}_{2}$ ridge waveguide are also fabricated and show fairly good performances.      

Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop

This paper describes a new implementation of a CMOS electrothermal frequency-locked-loop (FLL), whose output frequency is determined by the temperature-dependent phase shift of an electrothermal filter (ETF). The FLL maintains a constant phase shift in the ETF, and as a result drives it with a signal whose frequency is a well-defined function of temperature. Compared to a previous implementation, the FLL described here has significantly more loop gain, less electrical phase-spread, and is more suitable for full integration. Measurements on 16 samples (from one batch) show that the temperature dependence of the FLL's output frequency agrees very well with the known thermal properties of bulk silicon. The untrimmed spread of this frequency is less than $pm $0.45% ($3sigma $ ) from $-{hbox{40}}^{circ}{hbox{C}}$ to 100$^{circ} {hbox {C}}$, which corresponds to a temperature-sensing inaccuracy of less than $pm {hbox{0.7}},^{circ}{hbox{C}}$ ( $3sigma$).      

Soft Glass Equiangular Spiral Photonic Crystal Fiber for Supercontinuum Generation

An equiangular spiral photonic crystal fiber (ES-PCF) design in soft glass is presented that has high nonlinearity ( $gamma>5250 hbox{W}^{-1}cdothbox{km}^{-1}$ at 1064 nm and $gamma>2150 hbox{W}^{-1}cdothbox{km}^{-1}$ at 1550 nm) with a low and flat dispersion (${D}sim {hbox {0.8}} hbox{ps/km}cdothbox{nm}$ and dispersion slope $sim-0.7 hbox{ps/km}cdothbox{nm}^{2}$ at 1060 nm). The design inspired by nature is characterized by a full-vectorial finite element method. The ES-PCF presented improves over the mode confinement of triangular core designs and dispersion control of conventional hexagonal PCF, combining the advantages of both designs; it can be an excellent candidate for generating supercontinuum pumped at 1.06 $mu{hbox {m}}$.      

High Heat Flux Two-Phase Cooling in Silicon Multimicrochannels

This paper presents performances of two-phase cooling of a chip at very high heat flux with refrigerant R236fa in a silicon multimicrochannel heat sink. This heat sink was composed of 134 parallel channels, 67 $mu {hbox {m}}$ wide, 680 $mu {hbox {m}}$ high, and 20 mm long, with 92-$mu {hbox {m}}$ -thick fins separating the channels. The base heat flux was varied from 3 to 255 ${hbox {W/cm}}^{2}$ , the volume flow rate from 0.18 to 0.67 l/min, and the exit vapor quality from 0 to 80%. The working pressure and saturation temperature were set at 273 kPa and 25 $^{circ}{hbox {C}}$, respectively. The present database includes 1040 local heat transfer coefficients. The base temperature of the chip could be maintained below 52 $^{circ}{hbox {C}}$ while dissipating 255 ${hbox {W/cm}}^{2}$ with 10 $~^circ{hbox {C}}$ of inlet subcooling and 90 kPa of pressure drop. A comparison of the respective performances with an extrapolation of the present results shows that two-phase cooling should be able to cool the chip 13 K lower than liquid cooling for the same pumping power at a base heat flux of 350 ${hbox {W/cm}}^{2}$.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS

This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2$times$-oversampling phase-tracking CDR, implemented in 90$,$nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s realized in a single IC by the novel feature of a data rate selection logic. Input data are sampled with eight parallel differential master-slave flip-flops, where bandwidth enhancement techniques were necessary for 90 nm CMOS. Precise and low-jitter local clock phases are generated by an analog delay-locked loop. These clock phases are aligned to the incoming data by four parallel phase rotators. The phase-tracking loop of the CDR is realized as a digital delay-locked loop and is therefore immune against process tolerances. The CDR is able to track a maximum frequency deviation of ${pm }{hbox{615~ppm}}$ between incoming data and a local reference clock and fulfills the extended XAUI jitter tolerance mask. A bit error rate ${≪} hbox{10}^{-12}$ was verified up to 38 Gb/s using a 2$ ^{7} -$1 PRBS pattern. With a low power consumption per data rate of only 5.74 mW/(Gb/s) the CDR meets the specifications of the International Technology Roadmap for Semiconductors for 90$~$nm CMOS serial I/O-links at the maximal data rate of 44 Gb/s. The CDR occupies a chip area of 0.2 ${hbox{mm}}^{2}$ .      

Antenna-in-Package and Transmit–Receive Switch for Single-Chip Radio Transceivers of Differential Architecture

A fully differential architecture from the antenna to the integrated circuit is proposed for radio transceivers in this paper. The physical implementation of the architecture into truly single-chip radio transceivers is described for the first time. Two key building blocks, the differential antenna and the differential transmit–receive (T–R) switch, were designed, fabricated, and tested. The differential antenna implemented in a package in low-temperature cofired-ceramic technology achieved impedance bandwidth of 2%, radiation efficiency of 84%, and gain of 3.2 dBi at 5.425 GHz in a size of 15$times$15$times$1.6 ${hbox {mm}}^{3}$. The differential T–R switch in a standard complementary metal–oxide–semiconductor technology achieved 1.8-dB insertion loss, 15-dB isolation, and 15-dBm 1-dB power compression point ($P_{1,{hbox {dB}}}$) without using additional techniques to enhance the linearity at 5.425 GHz in a die area of 60$times$40 $mu{hbox {m}}^{2}$.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

A Dual-Band Self-Oscillating Mixer for -Band and -Band Applications

A self-oscillating mixer that employs both the fundamental and harmonic signals generated by the oscillator subcircuit in the mixing process is experimentally demonstrated. The resulting circuit is a dual-band down-converting mixer that can operate in $C$ -band from 5.0 to 6.0 GHz, or in $X$-band from 9.8 to 11.8 GHz. The oscillator uses active superharmonic coupling to enforce the quadrature relationship of the fundamental outputs. Either the fundamental outputs of the oscillator or the second harmonic oscillator output signals that exists at the common-mode nodes are connected to the mixer via a set of complementary switches. The mixer achieves a conversion gain between 5–12 dB in both frequency bands. The output 1-dB compression points for both modes of the mixer are approximately $-{hbox{5 dBm}}$ and the output third-order intercept point for $C$ -band and $X$ -band operation are 12 and 13 dBm, respectively. The integrated circuit was fabricated in 0.13-$mu {hbox{m}}$ CMOS technology and measures ${hbox{0.525 mm}}^{2}$ including bonding pads.      

Design and Analysis of a 0.8–77.5-GHz Ultra-Broadband Distributed Drain Mixer Using 0.13-$mu$m CMOS Technology

A compact and broadband 0.8–77.5-GHz passive distributed drain mixer using standard 0.13-$mu$ m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of ${hbox{5.5}} pm {hbox{1}}$ dB from 0.8 to 77.5 GHz with a compact size of 0.67$,times,$ 0.58 mm$^{2}$ . The output 1-dB compression point is ${-}{hbox{8.5}}$ dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption.