共查询到17条相似文献，搜索用时 46 毫秒
1.
张华 《固体电子学研究与进展》2014,(6)
提出了一种适合于低电压嵌入式闪存的灵敏放大器。该灵敏放大器采用了增强电流感应的方法,使得电源电压可以降到1.5V及其以下。灵敏放大器中采用的动态位线箝位电路可以提高位线预充速度并减小功耗。本电路在0.13μm的Flash工艺中实现。测试结果表明:提出的灵敏放大器在电源电压为1.5V时,访问时间是25ns;在电源电压为1.2V时,访问时间是32ns。 相似文献
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《固体电子学研究与进展》2016,(3)
提出了一种适合于低电源电压嵌入式闪存系统的高速的灵敏放大器电路。讨论了应用在这个灵敏放大器电路中的自箝位预充技术及自定时锁存技术。提出的灵敏放大器电路在0.11μm的嵌入式闪存平台上实现。测试结果表明:本文提出的灵敏放大器电路在1V的电源电压下达到6.4ns的访问时间。 相似文献
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《固体电子学研究与进展》2015,(1)
提出了一种适合于低电源电压嵌入式闪存系统的高速高抗干扰能力的灵敏放大器。讨论了应用在这个灵敏放大器中的多相位预充、自调节负载及新型的箝位技术。提出的灵敏放大器电路在0.18μm的嵌入式闪存平台上实现。测试结果表明:提出的灵敏放大器达到9ns的访问时间。 相似文献
4.
杨光军 《固体电子学研究与进展》2016,(3):240-244
提出了一种适合于低电源电压嵌入式闪存系统的高速的灵敏放大器电路。讨论了应用在这个灵敏放大器电路中的自箝位预充技术及自定时锁存技术。提出的灵敏放大器电路在0.11μm的嵌入式闪存平台上实现。测试结果表明:本文提出的灵敏放大器电路在1V的电源电压下达到6.4ns的访问时间。 相似文献
5.
提出了一种适合于低电源电压嵌入式闪存系统的高速高抗干扰能力的灵敏放大器。讨论了应用在这个灵敏放大器中的多相位预充、自调节负载及新型的箝位技术。提出的灵敏放大器电路在0.13 μm的嵌入式闪存平台上实现。测试结果表明,提出的灵敏放大器达到6 ns的访问时间。 相似文献
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A new low-voltage and high-speed sense amplifier is presented, based on a very simple direct current-mode comparison. It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage, low power and high precision. The proposed amplifier can sense a 0.5 μ A current gap and work with a lowest voltage of 1 V. In addition, the current power of a single amplifier is optimized by 15%. 相似文献
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提出了一种新型灵敏放大器,电路由单位增益电流传输器、电荷转移放大器及锁存器三部分组成。基于0.18μm标准CMOS单元库的仿真结果表明,与现有几种灵敏放大器相比,新型灵敏放大器具有更低的延时和功耗,在1.8 V工作电压、500 MHz工作频率、80μA输入差动电流以及DSP嵌入式SRAM6T存储单元测试结构下,每个读周期的延迟为728 ps,功耗为10.5fJ。与电压灵敏放大器相比,延迟减少约41%,功耗降低约50%;与常规电荷转移灵敏放大器相比,延迟减少约22%,功耗降低约37%;与WTA电流灵敏放大器相比,延迟减少11%,功耗降低31.8%。 相似文献
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一种快速、低压的电流灵敏放大器的设计 总被引：1，自引：0，他引：1
提出了一种快速和低工作电压的非挥发性存储器的电流灵敏放大器。该电路采用自控恒流预充电路提高灵敏放大器的放大速度。TSMC的0．18μm模型库的HSPICE仿真结果表明，电路在-40℃～125℃范围内有快速的读取速度，在1V工作电压和室温下，电路的读取时间是33ns。 相似文献
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随着微电子技术节点不断向前推进,非挥发性存储器(NVM)的容量迅速增大,对读取速度的要求也日益提高。通常,在大规模快闪存储器中采用页读取模式将多个比特的数据同时读取到缓存中,再从缓存中依次输出数据。这样等效于缩短读取周期,但也会遇到瞬态功耗过大的问题。作为改进措施,提出一种新型电流型灵敏放大器的预充方法,在传统灵敏放大器的基础上,采取多相位预充的方法,分时段对位线进行预充电,将瞬态大电流平均到整个预充周期,从而在保证低功耗的同时加大页读取的容量,提高读取速度。经验证,采用该方法的灵敏放大器具有较快的读取速度、较低的功耗,在3.3V工作电压下,电路的读取时间为7ns。 相似文献
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This paper presents a sense amplifier scheme for low-voltage embedded flash(eFlash)memory applications.The topology of the sense amplifier is based on current mode comparison.Moreover,an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current.The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process,and the sense time is 0.43 ns at 1.5 V,corresponding to a46% improvement over the conventional technologies. 相似文献
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Jiarong Guo 《半导体学报》2017,38(4):045001-5
A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃. 相似文献
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A new low-voltage and high-speed sense amplifier is presented,based on a very simple direct current-mode comparison.It adopts low-voltage reference current extraction and a dynamic output method to realize its performance indicators such as low voltage,low power and high precision.The proposed amplifier can sense a 0.5μA current gap and work with a lowest voltage of 1V.In addition,the current power of a single amplifier is optimized by 15%. 相似文献
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本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想. 相似文献
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In this article a new structure of the multifunction second-order frequency filter working in current mode is presented. The circuit solution employs voltage conveyors and programmable current amplifiers. The advantage of the proposed circuit is the possibility of mutually independent control of the quality factor Q and pole frequency f 0 using the active elements, current inputs at low-impedance and ground potential, realisation of the low-, high- and band-pass response without changing the circuit topology, low passive and active sensitivities. The frequency filter has been designed using the M-C signal flow graphs and its behaviour verified by OrCAD PSpice simulations. 相似文献
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A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts. 相似文献