集成电路圆片级芯片尺寸封装技术（WLCSP）

1技术创新性 集成电路圆片级芯片封装技术（WLCSP）及其产品属于集成创新,是江阴长电先进封装有限公司结合了铜柱凸块工艺技术及公司自身在封装领域的技术沉淀,开发出的区别于国外技术的新型圆片级芯片封装技术。     

圆片级封装的凸点制作技术

圆片级封装是一种先进的电子封装技术,近年来,圆片级封装技术的发展速度很快,主要应用于系统级芯片、光电器件和MEMS等.凸点制作是圆片级封装工艺的关键工序,目前凸点制作工艺方法有多种,重点介绍常用的电镀法、植球法和蒸发沉积法凸点工艺,分别介绍这三种凸点制作技术的工艺流程、关键技术.     

创新型超薄IC封装技术

圆片薄型化工艺技术的改进,以及对小型化、便携式产品的强烈的市场需求,共同推动了封装技术的创新。文中主要论述了与超薄型集成电路封装技术相关的薄型硅集成电路应用、超薄型圆片的制造、薄型化切割技术、同平面互连技术、倒装片装配及其可靠性问题。     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

基于晶圆键合的MEMS圆片级封装研究综述

为提升微机电系统（MEMS）器件的性能及可靠性,MEMS圆片级封装技术已成为突破MEMS器件实用化瓶颈的关键,其中基于晶圆键合的MEMS圆片级封装由于封装温度低、封装结构及工艺自由度高、封装可靠性强而备受产学界关注。总结了MEMS圆片级封装的主要功能及分类,阐明了基于晶圆键合的MEMS圆片级封装技术的优势。依次对平面互连型和垂直互连型2类基于晶圆键合的MEMS圆片级封装的技术背景、封装策略、技术利弊、特点及局限性展开了综述。通过总结MEMS圆片级封装的现状,展望其未来的发展趋势。     

圆片级封装技术展望

圆片级封装(Wafer-Level Packa-ging,WLP)已成为先进封装技术的重要部分。全圆片级封装虽然能够为芯片封装带来批量加工的规模经济效益,但由于系统集成方面的某些因素限制了其在主流应用中的推广。在圆片规模上开始加工,但结束于芯片规模的部分圆片级封装将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。     

圆片级封装技术——超CSPTM

文章论述了超CSPTM圆片级封装技术工艺。在封装制造技术方面此CSP封装技术的优越性在于其使用了标准的IC工艺技术。这不仅便于圆片级芯片测试和老炼筛选,而且在圆片制造末端嵌入是理想的。同时,文章也论述了超CSP封装技术的电热性能特征。     

MEMS器件封装技术

综述了微电子机械系统(MEMS)封装主流技术,包括芯片级封装、器件级封装和系统及封装技术进行了。重点介绍了圆片级键合、倒装焊等封装技术。并对MEMS封装的技术瓶颈进行了分析。     

几种新的封装工艺

文章介绍了几种新的封装工艺,如新型圆片级封装工艺——OSmium圆片级封装工艺,它能够把裸片面积减少一半;新型SiP封装工艺——Smafti封装工艺,它改进了传统SiP封装工艺,把传输速度提高了10倍;超薄型封装工艺,超薄型变容二极管和Wi-Fi系统功率放大器;CDFN封装工艺和RCP封装工艺等。     

圆片级封装

<正> 1 引言圆片级封装(WLP)是一种先进的封装技术,它的芯片互连与测试都是在圆片上完成的,之后再切片,进行倒装芯片组装。多年来,引线键合技术一直是在电路板或衬底上粘接集成电路的一种特殊手段。WLP 是采用引线链合的最新一代生产技术。WLP 正在取代某些高密度引线键合手段,近年内有望成为一种低成本标准技术。此外,由于倒装芯片互连具有极佳的电性能,因此它将是高密度系统的     

电子元器件封装技术发展趋势

晶圆级封装、多芯片封装、系统封装和三维叠层封装是近几年来迅速发展的新型封装方式,在推动更高性能、更低功耗、更低成本和更小形状因子的产品上,先进封装技术发挥着至关重要的作用。晶圆级芯片尺寸封装(WCSP)应用范围在不断扩展,无源器件、分立器件、RF和存储器的比例不断提高。随着芯片尺寸和引脚数目的增加,板级可靠性成为一大挑战。系统封装(SIP)已经开始集成MEMS器件、逻辑电路和特定应用电路。使用TSV的三维封装技术可以为MEMS器件与其他芯片的叠层提供解决方案。     

微电子封装的新进展领域及对SMT的新挑战

介绍了几种微电子新型封装材料,如LTCC、AIN、金刚石、AI-Sic和无铅焊接材料等,论述了正在发展中的新型先进封装技术,如WLP、3D和SIP等,并对封装新领域MEMS和MOEMS作了简介.最后,就这些新技术对SMT的新挑战作了些探讨.     

一种基于WLP封装的声表面波滤波器

以41°Y X切型铌酸锂作为基底材料,选择双T型阻抗元结构,采用晶圆级封装（WLP）技术,制作了一款相对带宽5.8%,最小插入损耗为-2.8 dB,体积为1.1 mm×0.9 mm×0.5 mm的小型化WLP封装声表面波滤波器。并研制了专用探卡,对封装后晶圆完成在线测试。测试结果表明,探卡测试结果与装配到实际电路的测试结果进行对比,两者吻合较好,解决了WLP封装声表面波滤波器测试难题。     

Multiple impact characterization of wafer level packaging (WLP)

Wafer level packaging (WLP) of connectivity RF components for mobile devices has emerged as a low-cost and high performance, enabling technology. WLP devices are electronic components with an exposed die that utilizes a ball pitch compatible with standard surface mount technology (SMT) equipment and common printed circuit board (PCB) design techniques. WLP allows the devices to be directly mounted to the PCB of portable devices. One concern of adopting WLP for mobile device applications is reliability under multiple dynamic loading conditions, such as phone drop, due to the fragile nature of the exposed silicon die and the unique packaging designs. A series of dynamic 4-point bend tests were conducted to evaluate the multiple impact reliability of WLP samples. The purpose of this work was to better understand the failure modes and actual reliability of WLP under uniaxial loading, which is commonly observed in mobile drop simulations and tests. The results have been applied to WLP failure prediction for the system-level drop test by using simulation technology.     

新型微电子封装技术

本论文综述了自二十世纪九十年代以来迅速发展的新型微电子封装技术,包括焊球阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和系统封装(SIP)等项技术。同时,叙述了微电子三级封装的概念。并对发展我国新型微电子封装技术提出了一些思索和建议。     

Microwave frequency crosstalk model of redistribution line patterns on wafer level package

As the operating frequency of systems increases above the gigahertz frequency range, the electrical performance of a package becomes more critical. Wafer level package (WLP) is a promising solution for future high-speed packaging needs. Because the length of the interconnection lines on the WLP is limited to die size, the WLP has a minimum number of electrical parasitic elements. Because the crosstalk generates significant unwanted noise in nearby lines, causing problems of skew, delay, logic faults, and radiated emission, the crosstalk phenomena is drawing more attention than ever among the electrical characteristics of the WLP. Consequently, the modeling of the crosstalk parameters of the WLP is very important when used in high-speed systems. In this paper, we first report the crosstalk model parameters of the WLP, especially for the redistribution layer. These can be easily embedded into SPICE circuit simulation. The model is represented by the distributed lumped circuit elements, such as the mutual capacitance and the mutual inductance. The crosstalk model was extracted from two-step on-wafer S-parameter measurements and was fitted to the measurements made at up to 5 GHz.     

现代圆片级封装技术的发展与应用

本文论述了圆片级封装的发展、优势、种类、应用、研究课题及产业化注意事项。     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

基于挠性基板的高密度IC封装技术

挠性印制电路技术迅速发展,其应用范围迅速扩大,特别是在IC封装中的应用受到人们的广泛关注。挠性印制电路在IC封装中的应用极大地推动了电子产品小型化、轻量化以及高性能化的进程。针对具体应用对象,文章分别介绍了挠性基板CSP封装、COF封装以及挠性载体叠层封装的基本工艺、关键技术、应用现状及发展趋势,充分说明了挠性印制电路和高密度布线对高密度IC封装的适用性。基于挠性基板的IC封装技术将会保持高速的发展,特别是挠性叠层型SIP封装技术具有广阔的应用前景。