漏雪崩应力下热载流子注入引起的MOSFET退变特性研究

本文对亚微米MOSFET在漏雪崩恒流应力(DAS)条件下热载流子注入引起的退变现象做了实验研究。实验结果表明:在一般的恒流应力条件下,栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特性起主要影响作用。恒流应力过程中,任何附加的电子注入都可使器件退变特性发生明显变化,实验结果还证实,漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴(SHH)注入技术,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响,讨论了不同应力条件下的阈值电压变化.阈值电压的漂移表明是正电荷陷入氧化层中,而热电子的存在是氧化层击穿的必要条件.把阳极空穴注入模型和电子陷阱产生模型统一起来,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的.研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡.认为栅氧化层的击穿是一个两步过程.第一步是注入的热电子打断Si一O键,产生悬挂键充当空穴陷阱中心,第二步是空穴被陷阱俘获,在氧化层中产生导电通路,薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的.     

衬底热空穴注入下的薄栅氧化层击穿特性

利用衬底热空穴 (SHH)注入技术 ,分别定量研究了热电子和空穴注入对薄栅氧化层击穿的影响 ,讨论了不同应力条件下的阈值电压变化 .阈值电压的漂移表明是正电荷陷入氧化层中 ,而热电子的存在是氧化层击穿的必要条件 .把阳极空穴注入模型和电子陷阱产生模型统一起来 ,提出了薄栅氧化层的击穿是与电子导致的空穴陷阱相关的 .研究结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .认为栅氧化层的击穿是一个两步过程 .第一步是注入的热电子打断 Si— O键 ,产生悬挂键充当空穴陷阱中心 ,第二步是空穴被陷阱俘获 ,在氧化层中产生导电通路     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hot-carrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性.测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移,并与单独HCI和NBT应力下的特性进行了对比.在这两种应力偏置条件下,pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强.由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场,使得器件特性严重退化.给出了NBT效应不断增强的HCI耦合效应的详细解释.     

漏雪崩应力热载流子注入引起的MOSFET退变特性研究

本对亚微米ＭＯＳＦＥＴ在漏雪崩恒流应力（ＤＡＳ）条件下热载流子注入引起的退变现象做了实验研究，实验结果表明：在一般的恒流应力条件下，栅氧化层中由空穴注入形成的空穴陷阱电荷对器件特起主要影响作用，恒流应力过程中，任何附加的电子注入都可使器件退变特性发生明显变化。实验结果还证实，漏雪崩应力期间形成的空穴陷阱电荷可明显降低器件栅氧化层的介质击穿特性。     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

pMOS器件的热载流子注入和负偏压温度耦合效应

研究了在热载流子注入HCI(hotcarrier injection)和负偏温NBT(negative bias temperature)两种偏置条件下pMOS器件的可靠性．测量了pMOS器件应力前后的电流电压特性和典型的器件参数漂移，并与单独HCI和NBT应力下的特性进行了对比．在这两种应力偏置条件下，pMOS器件退化特性的测量结果显示高温NBT应力使得热载流子退化效应增强．由于栅氧化层中的固定正电荷引起正反馈的热载流子退化增强了漏端电场，使得器件特性严重退化．给出了NBT效应不断增强的HCI耦合效应的详细解释．     

20V NLDMOS器件在关态雪崩击穿条件下的退化

对一种工作在关态雪崩击穿条件下的20V的NLDMOS器件的退化特性进行了研究。通过电流脉冲应力实验、TCAD软件仿真、以及电荷泵测试,提出了两种退化机制。第一种机制是N型漂移区中热空穴注入到氧化层中,在氧化层中形成固定正电荷;第二种机制是漂移区中界面态的增加引起的载流子迁移率下降。这两种机制都随着雪崩电流的增加而增强。     

半导体技术

TN301 02040526半导体量子阱中施主杂质态研究/贺卫国,蔡敏,阮文英(华南理工大学) 华南理工大学学报。-2001,29(12)。-31-33半导体量子阱的杂质离子可以位于量子阱的中心或偏离中心一定的距离d。该文用打靶法求解薛定谔方程,研究施主杂质的能谱随d的变化,发现具有相同角动量的能态具有相似的变化规律。图1表1参3(木)TN301 02040527应力导致的薄栅氧化层漏电流瞬态特性研究/刘红侠,郝跃(西安电子科技大学微电子所) 物理学报。-2001,50(9)。-1769-1773分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性。在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同。热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性。研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没。利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱。图4参10(午)     

低剂量率下MOS器件的辐照效应

对MOS器件在低剂量率γ射线辐射条件下的偏置效应进行了研究。对不同偏置及退火条件下MOS器件辐照后的阈值电压漂移进行了对比。结果表明，偏置在MOS器件栅氧化层内产生电场，增强了辐照产生电子-空穴对的分离，同时，影响了正电荷（包括空穴和氢离子）的运动状态；此外，偏置对退火同样有促进作用。     

Hot electron and hot hole degradation of UHV/CVD SiGe HBT's

We investigate the degradation in current gain and low-frequency noise of SiGe HBT's under reverse emitter-base stress due to hot electrons (forward-collector stress) and hot holes (open-collector stress). Contrary to previous assumptions we show that hot electrons and hot holes with the same kinetic energy generate different amounts of traps and hence have a different impact on device degradation. These results suggest that the accuracy of using forward-collector stress as an acceleration tool and reliability predictor must be carefully examined. We also present, for the first time, the effect of Ge profile shape on the reliability of SiGe HBT's, as well as discuss measurements on SiGe HBT's as a function of device geometry and temperature     

Hot carriers' effects in short channel devices

Experimental evidence for the impact of hot holes injection under pulsed voltage stress on the device degradation are presented. The transconductance lowering was supposed to be caused by an increase of the interface states density near the drain region. A field effect mobility decrease and an increase of the surface scattering factor by an amount larger for the shorter channel lengths were observed.     

A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress

Enhanced device degradation of low-temperature n-channel polycrystalline thin-film transistors (poly-silicon TFTs) under exposure to ac stress has been quantitatively analyzed. This analysis showed that degradation of the device characteristics of a single-drain (SD) TFT is greater under ac stress than under dc stress over an equivalent period. It was found that hot holes are strongly related to this greater severity of degradation. Moreover, a lightly doped drain (LDD) TFT is less strongly affected, and the effect is dominated by accumulated drain-avalanche hot-carrier (DAHC) stress. It was also found that differences between the electric field in the respective channel regions are responsible for the different degradation properties of SD and LDD TFTs. It was shown that the severe degradation under ac stress in an SD TFT is caused by increased DAHC stress, to which electrons emitted from the trap states when the TFT is turned off make significant contributions.     

Charge accumulation effects in InGaAs/GaAs [111]-oriented piezoelectric multiple quantum wells

We show that charge accumulation in piezoelectric [111]-oriented multiple quantum wells (MQWs), with average electric fields opposing the field in the barriers, inhibits the shift of optical transitions by externally applied electric fields. This effect is due to the screening of the average electric field as photogenerated electrons and holes drift towards the opposite edges in the MQW region due to this average field. The resulting dipole flattens the envelope potential and hence precludes the change of energy levels with variations of external voltage. This behavior has been observed in different device configurations employing InGaAs/GaAs MQW embedded in a p-i-n diode by low temperature photoluminescence (PL) and photocapacitance spectroscopies under different bias conditions. In addition to these ‘self-locked’ transitions we also observed other peaks in the PL spectra related to the charge accumulation effect and that are qualitatively explained using Hartree calculations.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2.5nm超薄栅短沟pMOSFETs在Vg=Vd/2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si-SiO2界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.     

在Vg=Vd/2应力模式下2.5nm氧化层pMOSFETs的新寿命预测模型

研究了2 .5 nm超薄栅短沟p MOSFETs在Vg=Vd/ 2应力模式下的热载流子退化机制及寿命预测模型.栅电流由四部分组成:直接隧穿电流、沟道热空穴、一次碰撞电离产生的电子注入、二次碰撞电离产生的空穴注入.器件退化主要是由一次碰撞产生的电子和二次碰撞产生的空穴复合引起.假设器件寿命反比于能够越过Si- Si O2 界面势垒的二次碰撞产生的二次空穴数目,在此基础上提出了一个新的模型并在实验中得到验证.     

Anomalous variations of OFF-State leakage current in poly-Si TFTunder static stress

Studies the anomalous variations of the OFF-state leakage current (I_OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I_OFF can be attributed to (1) I_OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and (2) I_OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (~(V_Gstress V_Dstress)/T _OX) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (~V_Dstress/L_CH)     

应力下LDD nMOSFET栅控产生电流退化特性研究

研究了LDD nMOSFET栅控产生电流在电子和空穴交替应力下的退化特性。电子应力后栅控产生电流减小,相继的空穴注人中和之前的陷落电子而使得产生电流曲线基本恢复到初始状态。进一步发现产生电流峰值在空穴应力对电子应力引发的退化的恢复程度与阈值电压和最大饱和漏电流不同。电子应力中陷落电子位于栅漏交叠区附近的沟道侧I区和LDD侧的II区中氧化层中。GIDL应力中,空穴注入进II区中和了陷落电子,使得产生电流的退化基本得到恢复,但这些空穴并未有效中和I区中的陷落电子,因此阈值电压和最大饱和漏电流退化恢复的程度较小,分别为20%和7%。     

Memory effects on piezoelectric InGaAs/GaAs MQW PIN diodes

Charge accumulation erects in piezoelectric multiple quantum well (MQW) InGaAs/GaAs PIN diodes grown on (111)B GaAs substrates have been studied regarding memory applications. Strain-induced piezoelectric fields allow new PIN structures with configurations of negative average electric field (NAF) active region. These new devices can store an electric dipole with spatially separated electrons and holes that have low recombination probability and thus long lifetimes. This produces a longrange screening of the field in the active region and hence a strong blue shift of the absorption band edge (maximum light transmission for reading purposes). Both a light pulse and a forward voltage pulse are able to create the dipole (data writing or charged device). The stored dipole can be removed by a reverse electrical pulse (data erasing or device discharge), resulting in a minimum light transmission across the device. Capacitance voltage and time resolved capacitance measurements, after single optical or electrical charging pulse at low temperature (20 K) have been used to determine the stored dipole behaviour. Capacitance transients analysis allowed study of the kinetics of the discharge process, which shows a non-exponential behaviour with storage times up to 10³ sec, suggesting very long time refresh cycles. Time resolved photocurrent has been used to check read and write capabilities giving on-off ratios up to 30.