Pulsed phase-locked loop technology improvements for greateraccuracy and expanded capabilities

This paper presents the design for a new pulsed phase-locked loop (PPLL) instrument. Earlier phase detection methods are analyzed for potential error sources, and an alternative phase detection method with fewer sources of error is described. This alternative method of phase detection is incorporated into a fully automated PPLL instrument. Data taken with the new system is compared to data taken with an earlier PPLL instrument. This comparison shows that the alternative phase detection does reduce error. The control loop is analyzed for stability and optimization, and a method of automating this optimization is presented. A method of wave-form acquisition using the automated PPLL that permits automatic location of the received echo is also described     

A new phase-locked loop used in a frequency synthesizer

A well-known contradiction in phase-locked frequency synthesizer design is between frequency resolution, on the one hand, and bandwidth of the phase-locked loop (PLL), on the other. To solve this problem, a technique that uses an algorithm that produces a group of different divide numbers to the programmable feedback frequency divider of PLL for each required output frequency is presented. The interference frequency at the output of the phase detector of PLL and the frequency resolution can then be set independent of each other. High resolution and wide bandwidth are achieved simultaneously, with a simple synthesizer design leading to savings in power consumed and device cost     

A reconfigurable high-frequency phase-locked loop

Reconfigurable phase-locked loops (PLLs) present the advantage of fast-frequency acquisition combined with narrow-noise bandwidth, since their parameters can be dynamically adjusted. High-frequency PLLs are generally implemented by means of analog circuits which are not easily reconfigured during operation. However, the five-port technique allows the discrimination of the phase difference between two microwave signals using a mixed circuit. In this paper the design of a PLL comprising a five-port based phase detector is presented. This system benefits from the phase-detector digital circuit to carry out the loop filtering. Simulation results for different conditions of noise and frequency acquisition are shown. We also present measurement results to confirm the simulations.     

Real-time fringe pattern demodulation with a second-order digital phase-locked loop

The use of a second-order digital phase-locked loop (DPLL) to demodulate fringe patterns is presented. The second-order DPLL has better tracking ability and more noise immunity than the first-order loop. Consequently, the second-order DPLL is capable of demodulating a wider range of fringe patterns than the first-order DPLL. A basic analysis of the first- and the second-order loops is given, and a performance comparison between the first- and the second-order DPLL's in analyzing fringe patterns is presented. The implementation of the second-order loop in real time on a commercial parallel image processing system is described. Fringe patterns are grabbed and processed, and the resultant phase maps are displayed concurrently.     

Fringe pattern demodulation with a two-frame digital phase-locked loop algorithm

A novel technique called a two-frame digital phase-locked loop for fringe pattern demodulation is presented. In this scheme, two fringe patterns with different spatial carrier frequencies are grabbed for an object. A digital phase-locked loop algorithm tracks and demodulates the phase difference between both fringe patterns by employing the wrapped phase components of one of the fringe patterns as a reference to demodulate the second fringe pattern. The desired phase information can be extracted from the demodulated phase difference. We tested the algorithm experimentally using real fringe patterns. The technique is shown to be suitable for noncontact measurement of objects with rapid surface variations, and it outperforms the Fourier fringe analysis technique in this aspect. Phase maps produced withthis algorithm are noisy in comparison with phase maps generated with the Fourier fringe analysis technique.     

A study on phase-noise reduction method in phase-locked loop systems

Experimental studies are carried out on phase noise and the correlation coefficient between the phase and average current noises of the voltage-controlled oscillator in phased-locked loop (PLL) systems. The precise phase stabilization technique is discussed, and new methods to reduce the phase noise are described in PLL systems, using the correlation.     

Fringe pattern demodulation with a two-dimensional digital phase-locked loop algorithm

A novel technique called a two-dimensional digital phase-locked loop (DPLL) for fringe pattern demodulation is presented. This algorithm is more suitable for demodulation of fringe patterns with varying phase in two directions than the existing DPLL techniques that assume that the phase of the fringe patterns varies only in one direction. The two-dimensional DPLL technique assumes that the phase of a fringe pattern is continuous in both directions and takes advantage of the phase continuity; consequently, the algorithm has better noise performance than the existing DPLL schemes. The two-dimensional DPLL algorithm is also suitable for demodulation of fringe patterns with low sampling rates, and it outperforms the Fourier fringe analysis technique in this aspect.     

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master?slave architecture with a precise master clock generator sending signals to phaselocked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.     

大气激光应急通信系统中的锁相环设计

在传统锁相环的基础上,提出并设计了一种数字锁相环,其在大气激光应急通信系统中的功能是用输入信号预处理得到的准同步信号去同步当地时钟信号,使之相位保持一致。该数字锁相环采用闭环反馈跟踪方法,并用 CPLD 器件予以实现。在 MAX PLUSⅡ环境下的仿真试验表明,该锁相环锁相误差小、抖动小、可靠性高;与传统锁相环相比,该设计编程方便,工作可靠。     

A novel flash fast-locking digital phase-locked loop: design and simulations

A flash digital phase-locked loop (DPLL) is designed using 0.18 μm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz?2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.     

水声通信中内嵌锁相环的格型均衡器

最小二乘格型（Least Squares Lattice,LSL）自适应均衡算法具有收敛速度快、算法复杂度低、对舍入误差不敏感等特点,适于应用在水下实时通信中。在LSL均衡算法的基础上,为增强对多普勒频移的跟踪能力,在均衡器中加入等效二阶锁相环（PLL）,提出了两种算法：后置PLL的LSL算法（LSL-PLL-post）和预置PLL的LSL算法（LSL-PLL-pre）。对RLS、LSL、LSL-PLL-post和LSL-PLL-pre四种算法进行了仿真,结果表明：PLL显著增强了LSL均衡器对多普勒频移的跟踪能力;在多径和多普勒环境下,LSL-PLL-pre是四种算法中性能最好的。湖试数据分析表明,LSL-PLL-pre算法性能略优于LSL-PLL-post算法,更具实用价值。     

集成锁相环在激光脉冲调制系统中的应用

锁相环由鉴相器、环路滤波器及压控震荡晶体组成,是一个能跟踪输入信号频率和相位的闭环自动控制系统。研制的激光脉冲调制系统采用锁相技术,以单片、集成锁相环代替分立元件,实现了片内鉴频和鉴相的功能。研制的腔倒空驱动器能够输出 4MHz, 800kHz, 400kHz, 80kHz,40kHz, 8kHz, 4kHz, 800Hz, 400Hz 等不同重复频率的脉冲信号,输出功率达到瓦级,满足了声光布拉格池的要求。该激光脉冲调制系统已经应用在皮秒时间相关单光子计数光谱仪系统中,取得了比较理想的效果。     

高频锁相激光干涉仪技术纳米定位系统

提出了一种基于高频相移电子电路驱动的压电陶瓷执行器和外差式迈克尔逊激光干涉仪的纳米位置控制方法,该方法结合双轴机械传输导轨组成了高精度大量程纳米定位系统.系统实现步长为4.945 nm的直线位移,步长的相对不确定度为1.6×10-9,1μm行程误差重复性为0.1 nm,5 mm往返行程误差重复性为0.4 nm.该方法对纳米技术与计量界在纳米刻度上的操作控制都是很有用的.     

A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS

In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4 X 0.5 mm². With the leakage suppression circuit, the peak-to-peak jitter and the rms jitter are 43 and 5.36 ps, respectively.The power is 17 mW for a 1.2 V supply.     

大三环天线校准自动定位装置

基于大三环天线系统工作原理,提出了大三环天线系统的校准方法,设计了大三环天线系统自动校准夹具,建立相应的校准系统。实验数据符合相关标准要求,证明校准系统的准确、可靠。     

Digital synchronous detector and frequency control loop for cesiumbeam frequency standard

A setup that includes a digital synchronous detector and a digital frequency control loop and is designed for use in a cesium beam frequency standard is described. It is based on the TMS 32010 signal microprocessor. When associated with a high-quality HP 5061A option four cesium beam tube, it makes it possible to achieve the same levels of short-term and medium-term frequency stability as its original analog counterpart. It is thus expected that the setup will fit the improved short- and long-term frequency stability capability of optically pumped cesium beam tubes     

Optical calibration phase locked loop for the Shuttle RadarTopography Mission

The Shuttle Radar Topography Mission (SRTM) is an interferometric synthetic aperture radar system that flew on the space shuttle in February 2000, SRTM has an inboard antenna in the shuttle cargo bay and an outboard antenna at the end of a 60-m mast, extending from the cargo bay. In order to meet the elevation mapping accuracy requirement, the relative phase delay between the radar signals received via the outboard channel, compared with the inboard channel has to be known to within 80 at 5.3 GHz. This paper describes the design solutions and constraints, the devices, the analysis, and validation used to implement an optical calibration loop for SRTM. The calibration method involves injecting a tone into one panel of the inboard antenna, and sending an optical copy of the tone via a fiber-optic cable to be injected into the outboard antenna. A portion of the optical signal is reflected off an outboard partial mirror and travels back via the fiber to the inboard calibration system. There, it is converted back into a radio frequency tone and its phase is compared with the phase of the original tone. As the temperature of the mast fiber changes, a phase error is detected in the phase comparator. This error is used to control a custom designed optical phase shifter connected in series with the mast fiber. This phase-locked-loop guarantees that the phase of the calibration tone at the outboard stages within 1° relative to the phase of the calibration tone at the inboard antenna     

Instrumental implementation of a neuronlike generator with spiking and bursting dynamics based on a phase-locked loop

An instrumental model of a neuron based on a phase-locked loop with a bandpass filter in the control loop is proposed. The main constructive elements of the system are described. The existence of different dynamic modes that are qualitatively similar to the spiking and bursting neuron dynamics has been experimentally demonstrated.