Design of low leakage process tolerant SRAM cell

In this paper, a novel 8 Transistor Static Random Access Memory (SRAM) cell is proposed to reduce the static power introduced by sub threshold and gate leakages, thus reducing the total power dissipation. The power dissipation of the proposed cell in standby mode has reduced considerably, compared to the conventional 6 Transistor SRAM cell and NC SRAM cell. A better stability is achieved in this cell under different process corners. The proposed technique reduces the standby power to 6.22 nW, which is almost negligible compared to that of a 6T SRAM cell (4.23 uW). Hence, the proposed cell is more suitable for standby mode operation. The total power of the proposed cell is reduced by 25.6% and the read-stability is increased by 40% compared to the conventional 6T SRAM cell. Cadence (Virtuoso) tools are used for simulation with gpdk 45-nm process technology.     

Variability aware low leakage reliable SRAM cell design technique

This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power dissipation. It also estimates read/write delay, read stability, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and other design metrics at the expense of 84% area overhead.     

Highly stable,low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at V_DD = 0.4 V with high read/write yields.     

Low standby leakage 12T SRAM cell characterisation

In this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.     

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode

The design of nanoscale static random access memory (SRAM) circuits becomes increasingly challenging due to the degraded data stability, weaker write ability, increased leakage power consumption, and exacerbated process parameter variations in each new CMOS technology generation. A new asymmetrically ground-gated seven-transistor (7T) SRAM circuit is proposed for providing a low leakage high data stability SLEEP mode in this paper. With the proposed asymmetrical 7T SRAM cell, the data stability is enhanced by up to 7.03x and 2.32x during read operations and idle status, respectively, as compared to the conventional six-transistor (6T) SRAM cells in a 65 nm CMOS technology. A specialized write assist circuitry is proposed to facilitate the data transfer into the new 7T SRAM cells. The overall electrical quality of a 128-bit×64-bit memory array is enhanced by up to 74.44x and 13.72% with the proposed asymmetrical 7T SRAM cells as compared to conventional 6T and 8T SRAM cells, respectively. Furthermore, the new 7T SRAM cell displays higher data stability as compared to the conventional 6T SRAM cells and wider write voltage margin as compared to the conventional 8T SRAM cells under the influence of both die-to-die and within-die process parameter fluctuations.     

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Power dissipation,speed and stability are the most important parameters for multiple-valued SRAM design.To reduce the power consumption and further improve the performance of the ternary SRAM cell,we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs).The performance is simulated in terms of three criteria including standby-power,delay (write and read) and stability (RSNM).Compared to the novel ternary SRAM cell,our results show that the average standby-power,write and read delay of the proposed cell are reduced by 78.1％,39.6％ and 58.2％,respectively.In addition,the RSNM under process variations is 2.01 × and 1.95× of the conventional and novel ternary SRAM cells,respectively.     

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

We have used a 5-metal 0.18-μm CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-μm gate length     

低位线摆幅的低功耗SRAM设计

本文提出了一种低位线摆幅（LVBS）的低功耗SRAM结构。这种SRAM采用电荷分享方法降低线电压幅值，在写操作时使得位线电压摆幅减少了50％，从而显著降低了位线动态功耗。同时本文还分析了由于位线电压降低带来的静态噪声容限（SNM）等问题。实验结果表明相比较常规SRAM，LVBS SRAM可以节约30％的动态功耗。     

130nm工艺极低泄漏电流亚阈值SRAM存储单元设计

本文提出一款工作在亚阈值（200 mV）区域且具有极低泄漏电流的亚阈值SRAM存储单元。该存储单元采用自适应泄漏电流切断机制,该机制在没有带来额外的动态功耗和性能损失的前提下,同时降低动态操作（读/写操作）和静态操作时的泄漏电流。差分读出方式和可配置操作模式的应用,使得本文设计在亚阈值条件下（200 mV）仍然保持足够的鲁棒性。仿真结果表明,相比于参考文献中的亚阈值存储单元本文设计具有：（1）在不同的工艺角下,均具有较大的读噪声容限和保持噪声容限;（2）在动态操作和静态操作时均具有极低的泄漏电流。最后,我们将该存储单元成功的应用于IBM 130nm工艺下的一款 bits存储阵列中,测试结果表明该存储阵列可以在200 mV电源电压条件下正常工作,所对应功耗（包括动态功耗和静态功耗）仅0.13 μW,是常规六管存储单元功耗的1.16%。     

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.     

RTD/HFET low standby power SRAM gain cell

A 50-nW standby power compound semiconductor tunneling-based static random access memory SRAM (TSRAM) cell is demonstrated by combining ultralow current-density resonant-tunneling diodes (RTDs) and heterostructure field-effect transistors (HFETs) in one integrated process on an InP substrate. This power represents over two orders of magnitude improvement over previous III-V static memory cells. By increasing the number of vertically integrated RTD's we obtain a 100 nW tri-state memory cell. The cell concept applies to any material system in which low current-density negative differential resistance devices are available     

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power     

基于低信息泄露协商算法的无线信道密钥生成方案

针对无线信道生成密钥方法在信息协商中的信息泄露问题,提出了低信息泄露Cascade算法。通过构造传统Cascade协商过程的密钥协商过程矩阵,推导了合法用户所得密钥中安全的信息量,改进了Cascade算法;结合符号定时同步预处理以及高精度参数估计得到了一个完整的密钥生成方案。基于实测数据的分析结果表明,符号定时同步预处理能有效降低初始密钥不一致率;在协商成功率、密钥生成速率、密钥随机性、安全性等方面,低信息泄露Cascade协商算法与传统Cascade算法相比综合性能更优。     

Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage current in idle mode. In read operation, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In write operation, a negative bias on the cell facilitates to change contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates 2× higher read stability while bearing 20% better write-ability at 1.2 V typical condition and a reduction by 45% in leakage power consumption compared to the standard 6T cell. Results of the bit-cell architecture were also compared to the dual-port 8T SRAM cell. The stability enhancement and leakage power reduction provided with the proposed cell are confirmed under process, voltage and temperature variations.     

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel nine transistor (9T) CMOS SRAM cell design at 32 nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution at array-level, a novel write bitline balancing technique is proposed to reduce the leakage current. By optimizing its size and employing the proposed write circuit technique, 33% power dissipation saving is achieved in memory array operation compared with the conventional 6T SRAM based design. A new metric that comprehensively captures all of these figures of merit (and denoted to as SPR) is also proposed; under this metric, the proposed 9T SRAM cell is shown to be superior to all other cell configurations found in the technical literatures. The impact of the process variations on the cell design is investigated in detail. HSPICE simulation shows that the 9T SRAM cell demonstrates an excellent tolerance to process variations comparing with the conventional SRAM cells.     

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

We designed a logic-library-friendly SRAM array. The array uses rectangular-diffusion cell (RD cell) and delta-boosted-array-voltage scheme (DBA scheme). In the RD cell, the cell ratio is 1.0, and it reduces the imbalance of the cell ratio. A low supply voltage deteriorates the static noise margin, however, the DBA scheme compensates it. Using the combination of RD cell and DBA scheme, a 32-kB test chip achieves 0.4-V operation at 4.5-MHz frequency, 140-/spl mu/W power dissipation, and 0.9-/spl mu/A standby current.     

A fully distributed replica allocation scheme for an opportunistic network

An opportunistic network (OPPNET) consists of diverse mobile nodes with various mobility patterns. Numerous mobility patterns and the resource constraints of mobile nodes lead to network partitioning that result in system performance degradation including low data accessibility. In a traditional mobile ad hoc network (MANET) which is similar to an OPPNET, replica allocation schemes have been proposed to increase data accessibility. Although the schemes are efficient in a MANET, they may not be directly applicable to an OPPNET because the schemes are based on a grouping of mobile nodes. It is very difficult to build groups based on network topology in an OPPNET because a node in an OPPNET does not keep its network topology information. In this paper, we propose a novel replica allocation scheme for an opportunistic network called the Snooping-based Fully Distributed replica allocation scheme. The proposed scheme allocates replicas in a fully distributed manner without grouping to reduce the communication cost, and fetches allocated replicas utilizing a novel candidate list concept to achieve high data accessibility. In the proposed scheme, a node can fetch replicas opportunistically based on the candidate list. Consequently, the proposed replica allocation scheme achieves high data accessibility while reducing the communication cost significantly. Extensive simulation results demonstrate that the proposed scheme reduces the communication cost and improves data accessibility over traditional schemes.     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

The radiation induced soft errors have become one of the most important and challenging failure mechanisms in modern electronic devices. This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM). Analysis for 32 nm and 45 nm technology nodes is carried out. It is inferred from the paper that the proposed SRAM cell outperforms over DICE latch in terms of fault tolerance of external data and control lines, power dissipation and fast recovery when exposed to radiation for both the technology nodes. This is primarily due to the addition of extra transistors used to neutralize the effect of single event upset without affecting normal operations. Transistor count increase the area and write delay by 7% and 20% respectively over that of DICE latch. While read delay decreases by 14% for the proposed SRAM cell.