A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs

We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications.     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Analysis and control of floating-body bipolar effects in fullydepleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible     

SOI高压MOSFET的电流-电压特性模拟

在不同漂移区浓度分布下 ,通过二维数值模拟充分地研究了薄膜 SOI高压 MOSFET击穿电压的浓度相关性 ,指出了击穿优化对 MOSFET漂移区杂质浓度分布的要求。分析了MOSFET的电场电位分布随漏源电压的变化 ,提出寄生晶体管击穿有使 SOI MOSFET击穿降低的作用。     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

Study of the extended p+ dual source structure foreliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p⁺ dual source SOI MOSFET are reported. It is shown that the presence of the extended p ⁺ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p⁺ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's     

Single-transistor-latch-induced degradation of front- andback-channel thin-film SOI transistors

The front- and back-channel transistor characteristics in thin-film silicon-on-insulator (SOI) MOSFETs have been studied before and after front-channel hot-carrier stress resulting from single-transistor latch. This stress causes the following significant changes: (a) a reduction of the front-channel current for a given gate voltage, (b) an increase in front-channel drain-source breakdown voltage when measured in the reverse mode, and (c) a decrease in the back-channel transconductance. These changes can be attributed to the hot-carrier induced interface traps on both front and back interfaces near the drain junction     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale CMOS and SOI devices

In this paper, we investigate the threshold voltage fluctuation for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) and silicon-on-insulator (SOI) devices. The threshold voltage fluctuation comes from random dopant and short channel effects. The random-dopant-induced fluctuation is due to the random nature of ion implantation. The gate-length deviation and the line-edge roughness are mainly resulted from the short-channel effect. For the SOI devices, we should also consider the body thickness variation. In our investigation, the metal gate with high-κ material MOSFET is a good choice to reduce fluctuation of threshold voltage when comparing to the poly gate MOSFET and thin-body SOI devices.     

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage     

A quasi-SOI power MOSFET for radio frequency applications formed byreversed silicon wafer direct bonding

A quasi-SOI power MOSFET for radio frequency (RF) applications was fabricated by reversed silicon wafer direct bonding (RSDB). Its breakdown voltage was more than twice that of the conventional SOI power MOSFET and its other dc characteristics were almost the same. Its maximum oscillation frequency was about 15% higher than that of the conventional SOI power MOSFET. The power-added efficiency (PAE) of the quasi- SOI power MOSFET was higher than the SOI one. It showed excellent PAE of 68% at a drain bias of 3.6 V     

Analysis of drain breakdown voltage in SOI n-channel MOSFETs

The reduction of drain breakdown voltage in SOI nMOSFETs with floating substrate is related to the presence of a parasitic n-p-n bipolar structure, the base of which is the floating body of the device. reduction of breakdown voltage (compared to the case where a body contact is used) is shown to be dependent on both channel length and minority carrier lifetime in the SOI material. Conversely, it is shown that mere measurement of MOSFET breakdown voltages can be used to extract the minority carrier lifetime in the SOI material.<>     

Enhanced breakdown voltage and reduced self-heating effects in thin-film lateral bipolar transistors: Design and analysis using 2-D simulation

In this work, we present our two-dimensional numerical simulation studies and analysis of the enhanced breakdown and self-heating characteristics of a new collector-tub three-zone step doped thin-film lateral bipolar transistor (CT-SLBT) on silicon-on-insulator (SOI), which shows enhanced breakdown voltage as high as 80% when compared with that of the conventional uniformly doped lateral bipolar transistor (LBT) on SOI. The design issues and the reasons for the improved performance are discussed in detail.     

Analysis of the latch and breakdown phenomena in N and P channelthin film SOI MOSFET's as a function of temperature

A study of the latch and breakdown phenomena in thin film N- and P-channel SOI MOSFET's is performed as a function of temperature. For P-type MOSFET's, for which no investigation of the parasitic bipolar transistor has been carried out, we show that latch problems are observed in the subhalf-micrometer range, while this feature is emphasized in the micrometer range for N-channel transistors. In addition, it is demonstrated by theoretical considerations and experimental results that these parasitic effects are strongly reduced at liquid nitrogen temperature and vanish almost entirely at liquid helium temperature. Similar improvements are obtained at low temperature in both N and P-channel SIMOX MOSFET's     

RF power LDMOSFET on SOI

We have fabricated a SOI laterally diffused MOSFET that is designed for use in radio frequency power amplifiers for wireless system-on-a-chip applications. The device is fabricated on a thin-film SOI wafer using a process that is suitable for integration with SOI CMOS. An under-source body contact is implemented and both a high breakdown voltage and a high f_t are attained. The device performance compares favorably with bulk silicon rf power MOSFETs. For a gate length of 0.7 μm the device f_t is 14 GHz, f_max is 18 GHz, and the breakdown voltage approaches 25 V