SoC嵌入式flash存储器的内建自测试设计

深亚微米技术背景下，嵌入式存储器在片上系统芯片(system-on-a-chip，SoC)中占有越来越多的芯片面积．嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现，并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源，以保证满足测试过程中的功耗限制，同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。     

Symmetry Measure for Memory Test and Its Application in BIST Optimization

Programmable Built-in Self-Test (BIST) has been widely used for testing embedded memories. The main disadvantage of having programmability on BIST circuits is the size of Test Algorithm Register (TAR) that becomes very crucial in case of complex test algorithms. To optimize Programmable BIST hardware symmetric March tests are usually used in BIST engines. On the other hand, the used definitions do not reflect completely the existing symmetry in test algorithms and they also do not reflect the fact that the level of symmetry in a given test algorithm can be measured. A new method of symmetry measurement for memory test algorithms and a corresponding metric are introduced. A dependency between symmetry measure and BIST optimization range is analyzed. Optimization experiments that have been done for a number of well-known test algorithms show that the BIST hardware gain could reach 48%. However, the time overhead is negligible in comparison with the hardware gain. The experiments also show that starting from some point a monotone dependency between symmetry measure and BIST hardware area exists.     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。     

Simultaneous Static Testing of A/D and D/A Converters Using a Built‐in Structure

Static testing of analog‐to‐digital (A/D) and digital‐to‐analog (D/A) converters becomes more difficult when they are embedded in a system on chip. Built‐in self‐test (BIST) reduces the need for external support for testing. This paper proposes a new static BIST structure for testing both A/D and D/A converters. By sharing test circuitry, the proposed BIST reduces the hardware overhead. Furthermore, test time can also be reduced using the simultaneous test strategy of the proposed BIST. The proposed method can be applied in various A/D and D/A converter resolutions and analog signal swing ranges. Simulation results are presented to validate the proposed method by showing how linearity errors are detected in different situations.     

Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Application-specific integrated circuits (ASICs) and high-performance processors such as Itanium and Compaq Alpha use a total of almost 75% of chip real estate for accommodating various types of embedded (or on-chip) memories. Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits. This tutorial underlines the need for appropriate testing and reliability techniques for the present to the next generation of embedded RAMs. Topics covered include: reliability and quality testing, fault modeling, advanced built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques for high-bandwidth embedded RAMs.     

Effective march algorithms for testing single-order addressed memories

Today's commonly used macro generators provide for read/write memories of type SRAM, Register File, Multi-Port RAM, Single-Order Addressed Memory (e.g. FIFO), CAM (Content Addressable Memory), etc. In addition to automatically generating the required momory, the appropriate test, which may be applied externally or internally as a BIST, has to be determined.Current literature provides tests for most memory types; however, tests for single-order addressed (SOA) memories, whereby the address can only change in one direction (e.g. from address 0 ton-1) have not been published yet. SOA memories are used in FIFOs and in applications where the BIST area overhead and/or speed penalty for normal (dual) order addressing are not acceptable.This article illustrates the testing problems and presents a family of march algorithms optimized for testing SOA memories.     

An Efficient Built‐in Self‐Test Algorithm for Neighborhood Pattern‐ and Bit‐Line‐Sensitive Faults in High‐Density Memories

As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.     

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.     

SOC混合信号测试难题的解决策略

缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法.     

"龙腾"S2微处理器测试结构设计

介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求.     

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level

Test power requirements for complex components are becoming stringent. The purpose of this paper is to reuse a recently proposed RT (Register Transfer) Level test preparation methodology to drive innovative Low-Energy (LE)/Low-Power (LP) BIST solutions for digital SoC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of partially specified input vectors (masks), leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. The methodology is referred as masked-based BIST, or m-BIST. BIST quality is evaluated considering three attributes: test effectiveness (TE), test length (TL) and test power (TP). LE BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The energy and power of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.     

Decentralized BIST Methodology for System Level Interconnects

This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.     

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2-μm CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW     

一种嵌入式RAM的BIST设计

本文分析了嵌入式RAM的传统测试方法和内建自测试(BIST)方法,提出了一种新的BI ST设计方案,该设计方案具有测试生成快,节约测试成本等优点.     

Parallel BIST architecture for CAMs

A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved     

一款雷达信号处理SOC芯片的存储器内建自测试设计

内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障.