Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Ultra-shallow junction formation using silicide as a diffusionsource and low thermal budget

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using SADS (silicide-as-diffusion-source) and ITS (ion-implantation-through-silicide processing) of 45-nm CoSi₂ films (3.5 Ω/□) using a low thermal budget. The best junctions of either type were made by moderate 10-s RTA (rapid thermal annealing) at 800°C, where the total junction depth, counting the silicide thickness, is believed to be under 60 nm. Diffusion-limited current predominated down to 50°C in junctions made under these conditions. The initial implantation energy had only a minor effect on the junction leakage, where shallower implants required slightly higher temperatures to form low leakage diodes, resulting in diodes which were somewhat more susceptible to shorting during silicide agglomeration at high temperatures. The ITS scheme, where dopant is implanted slightly beyond the silicide, gives an equally low leakage current. Nevertheless, the ITS scheme gives deeper junctions than the SADS process, and it is difficult to control the position of the ITS junction due to silicide/silicon interface fluctuations     

Field emission characteristics of CoSi2/TaN-coatedsilicon emitter tips

This work has improved the emission characteristics of Si emitter tips by coating a CoSi₂/TaN bilayer on the tips. The CoSi₂ layer was grown in situ by a reactive chemical-vapor deposition of cyclopentadienyl dicarbonyl cobalt at 650°C. The TaN was then deposited on the CoSi₂ layer at 550°C by a reactive sputtering of Ta with N as a reactive gas. The CoSi₂/TaN-coated emitters showed a lower turn-on voltage and higher emission current than the CoSi₂- or TaN-coated emitters due to the low work function by TaN and the easy transport of electron by CoSi₂ with low resistivity. The long-term emission stability of CoSi₂/TaN-coated Si emitter was as good as TaN-coated emitter     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Electrical characteristics of TiB2 for ULSI applications

The work function of TiB₂ was measured using Fowler-Nordheim tunneling in MOS capacitors, Schottky diode current measurements, capacitance-voltage techniques, and contact resistance. The resulting data place the Fermi level of TiB₂ about 0.9 eV below the silicon conduction band. Given this barrier height, Schottky diodes of TiB₂/p-Si exhibit ohmic characteristics, but the contact resistance of TiB₂ to n⁺ junctions is an order of magnitude higher than the generally desired value. Boron outdiffusion from TiB₂ into underlying silicon was observed at temperatures of 1000°C and greater. Boron diffusion from TiB₂ into silicon above 1000°C is enhanced compared to the conventionally accepted value of the boron diffusivity     

A manufacturable process to improve thermal stability of 0.25-μmcobalt silicided poly gate

A CoSi₂ salicidation process using a thin titanium capping layer is developed to improve the thermal stability of deep submicron CoSi₂/poly stacks. 50 nm CoSi₂ was uniformly formed on 0.25-μm wide poly lines. The electrical results show that the lines formed by a capping process using Ti can withstand higher thermal treatment (750° C for 30 min) without significant degradation. This work shows that the modified CoSi₂ process should be considered for 0.25-μm CMOS applications     

Impact of nitrogen (N2+) implantation intopolysilicon gate on thermal stability of cobalt silicide formed onpolysilicon gate

A novel process which uses N₂⁺ implantation into polysilicon gates to suppress the agglomeration of CoSi₂ in polycide gated MOS devices is presented. The thermal stability of CoSi₂/polysilicon stacked layers can be dramatically improved by using N₂⁺ implantation into polysilicon. The sheet resistance of the samples without N₂⁺ implantation starts to increase after 875°C RTA for 30 s, while the sheet resistance of CoSi₂ film is not increased at all after 950 and 1000°C RTA for 30 s if the dose of nitrogen is increased up to 2×10¹⁵ cm^-2 and 6×10¹⁵ cm², respectively, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed. It is found that the transformation to CoSi₂ from CoSi is impeded by N₂⁺ implantation such that the grain size of CoSi₂ with N₂⁺ implantation is much smaller than that without N₂⁺ implantation. As a result, the thermal stability of CoSi₂ is significantly improved by N₂⁺ implantation into polysilicon     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

Tantalum nitride-p-silicon high-voltage Schottky diodes

Rectifying contacts between TaN and p-silicon with very high reverse breakdown voltage (V_BR >700 V) without using any guard ring have been realized. Barrier heights of TaN to both p-type silicon and n-type silicon have been measured at 0.68 and 0.48 eV, respectively. The breakdown voltage V_BR of TaN to p-silicon diodes, as deposited, is ~400 V and decreases to less than 200 V after annealing in hydrogen at 450°C for 30 min. On the other hand, annealing in a nitrogen ambient at 450°C for 30 min. increases the V_BR of these diodes to more than 700 V. An explanation for the difference in V_BR is sought in terms of the structural/chemical changes introduced at the interface by the annealing process. The high forward drop of TaN to p-silicon diodes (>1 V at 10 mA) results from the high substrate resistance and the probe contact resistance, and it is being optimized     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

SiC/Si heterojunction diodes fabricated by self-selective and byblanket rapid thermal chemical vapor deposition

SiC/Si heterojunction diodes have been fabricated by two different rapid thermal chemical vapor deposition (RTCVD) processes: a localized self-selective growth and blanket growth. The self-selective growth of crystalline cubic (β) SiC was obtained by propane carbonization of the Si substrate in regions unprotected by an SiO₂ layer, producing planar diodes. Mesa diodes were fabricated using the blanket growth of polycrystalline β-SiC produced by the decomposition of methylsilane (CH₃SiH₃). The SiC/Si heterojunction diodes show good rectifying properties for both device structures. Reverse breakdown voltage of 50 V was obtained with the self-selective SiC/Si diode. The mesa diodes exhibited even higher breakdown voltages (V_br) of 150 V and excellent ideality factors of 1.06 at 25°C. The high V_br and good forward rectifying characteristics indicate that the SiC/Si heterojunction diode represents a promising approach for the fabrication of wide-gap emitter SiC/Si heterojunction bipolar transistors     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Characteristics of LPCVD WSi2/n-Si Schottky contacts

Detailed current-voltage and capacitance-voltage characteristics of low-pressure chemical vapor deposited (LPCVD) WSi₂/n-Si Schottky contacts are reported in the temperature range of 21 to 170°C. The diode ideality factor n was found to decrease from a value of 1.46 to 1.15 as temperature was increased. Schottky barrier height φ_B, on the other hand, was found to increase from 0.72 to 0.86 V with temperature. These results suggest that diode characteristics are affected by surface and bulk effects, especially at lower temperatures. High-resolution transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy analyses revealed isolated regions of oxynitride at the silicide/silicon interface that are predominantly located where silicide grain boundaries intersect the silicon surface     

Characteristics of planar n-p junction diodes made bydouble-implantations into 4H-SiC

Double implantation technology consisting of deep-range acceptor followed by shallow-range donor implantation was used to fabricate planar n⁺-p junction diodes in 4H-SiC. Either Al or B was used as the acceptor species and N as the donor species with all implants performed at 700°C and annealed at 1650°C with an AlN encapsulant. The diodes were characterized for their current-voltage (I-V) and capacitance-voltage (C-V) behavior over the temperature range 25°C-400°C, and reverse recovery transient behavior over the temperature range 25°C-200°C. At room temperature, the B-implanted diodes exhibited a reverse leakage current of 5×10^-8 A/cm² at a reverse bias of -20 V and a carrier lifetime of 7.4 ns     

Ti-Si-N diffusion barriers between silicon and copper

Thin films of Ti-Si-N, reactively spattered from a Ti₅Si₃ target, are assessed as diffusion barriers between silicon substrates and copper overlayers. By tests on shallow-junction diodes, a 100 nm Ti₃₄Si₂₃N₄₃ barrier is able to prevent copper from reaching the silicon substrate during a 850°C/30 min anneal in vacuum. A 10 nm film prevents diffusion up to 650°C/30 min. By high-resolution transmission electron microscopy, Ti₃₄Si₂₃N₄₃ predominantly consists of nanophase TiN grains roughly 2 nm in size     

Thin films of CoSi2 on Si1−yCy substrate layers

The reaction of Co with epitaxial Si_1−yC_y(001) films is investigated with regard to dependence on annealing temperature and C concentration y. Resistance measurements and RBS analysis reveal a small increase in the disilicide formation temperature. The electrical properties are very similar for thin CoSi₂ films grown at 650°C on Si_0.999C_0.001 and on Si. Whereas the CoSi₂ is fully polycrystalline on Si(001), partially oriented CoSi₂ has been observed on C-containing substrate layers. An increase of the number of epitaxially grown CoSi₂ crystallites has been observed with increasing C concentration.     

N-SixC1-x/P-Si diode fabricated using silane,1,1,1-trichloroethane and arsine at low temperatures

A novel method for depositing Si_xC_1-x alloys on silicon, based on the silane and 1,1,1-trichloroethane gas system, has been investigated in an inexpensive hot-wall horizontal LPCVD reactor. Temperatures in the range of 650 to 800°C and in situ doping using arsine were used successfully. The film characteristics were evaluated using electron spectroscopy for chemical analysis (ESCA) (XPS), Fourier transform infrared spectroscopy (FTIR), and optical absorption. N⁺-P⁺ heterojunctions with low reverse leakage current and a forward-bias ideality factor of 1.55 were successfully fabricated     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs