A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.     

面向DSP应用的可重构计算

DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣.因此出现了一种新的计算模式-可重构计算.由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究.本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考.     

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

一种适用于空间飞行器的可重构信息处理平台硬件设计

在我国空间通信技术取得巨大发展的今天,对空间飞行器电子设备功能可重构、可升级、运行代码可更换的需求越来越多。分析了空间辐射效应对高性能数字信号处理器（DSP）和SRAM型FPGA的影响,提出了一种适用于空间飞行器上的可重构信息处理平台的硬件设计方法,具有可重构、可在线升级运行代码的特点。该硬件架构计由高性能DSP和高可靠性的反熔丝FPGA为主要组成,提出了这种架构对抗空间单粒子效应的方法。该电路设计方法可以为空间飞行器通信设备的设计提供参考。     

Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding

A novel reconfigurable sequential decoder architecture based on the Fano algorithm is presented in which the constraint length, the threshold spacing, and the time-out threshold are all run time reconfigurable. To maximize decoding performance, a maximum possible backward depth (of a whole frame) is performed. This is achieved by using shift registers combined with memory to store the information of an entire visited path. A field-programmable gate array) prototype of the decoder is built and actual hardware decoding performances in terms of decoding speeds, bit error rates (BERs), and buffer overflow rates, are obtained and comparisons made. To overcome the decoding delay that is inherent in sequential decoders, a hybrid scheme, including simple block codes and cyclic redundancy check is proposed to limit the number of backward search operations that the sequential decoder has to execute. As a result, a significant reduction in decoding delay and buffer overflow rate is achieved while maintaining comparative decoding performance in terms of BER     

可重构硬件芯片级故障定位与自主修复方法

 外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.     

模拟型演化硬件中可重构器件的比较研究

演化硬件的研究者受困于满足可演化要求的灵活可重构硬件平台的匮乏.一方面,虽然现有商用可重构平台多数具有动态可局部重构能力,但是其设计目的不是用来研究演化硬件的.另外一方面,用户定制的面向演化硬件研究的芯片没有商用化,而且也不太可能在最近走向商用市场.本文研究了两类用来进行模拟演化硬件研究的可重构器件:商用的现场可编程模拟阵列和用户定制的现场可编程三极管阵列.通过比较研究,作者认为在FPTA类定制用于演化的可重构平台商用化之前,在FPAA平台上开展EHW的研究是有意义的,因为FPAA已经具有充分灵活的重构接口和充足的可重配置资源.     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

面向仪表的嵌入式DSP硬件平台

实现了一种基于DSP技术的仪表硬件平台并对其性能进行了实验分析.实验表明,该平台具有较快的数据采集速度、较高的运算能力和精度,能够完成实时数据的采集和处理;而且平台灵活性好,可实现多种类型信号的采集和处理.     

基于联合处理的硬件可重构SDR平台

随着移动通信领域出现了多个不同的标准,尤其是3G时代的到来,不同标准的终端之间的互联互通问题日益突出。本文利用联合处理的方法,提出了硬件可重构的软件无线电平台,通过改变系统的特性来快速适应不同的通信体制。这一平台通过在三个维度上应用联合处理方法：处理手段上的软硬件联合处理;处理域上射频、中频和基带联合检测与识别;在功能分类上的传输、接入、安全、重构四种功能合作。这一平台基于现有技术的水平,高效的实现了包含射频前端在内的多种通信体制的可重构。     

DSP算法的硬件实现

在图象处理的某些应用领域中，既要求系统有实时性，又要降低成本、减小体积。本文提出了DSP算法的硬件实现技术，并就直方图、模板匹配、数字滤波、中值滤波4种方案做了详细说明。     

音频专用DSP核的硬件循环设计

介绍了一个音频专用DSP核的硬件循环设计.该设计能实现单条指令和多条指令的硬件循环,并且由同一个电路实现,具有相同的指令格式,并支持最多4重嵌套的硬件循环.基于FPGA开发平台进行实验验证,结果表明,该设计能够正确高效地实现循环操作,为音频专用DSP核实现音频解码提供必要的支持.     

DSP硬件等待状态发生器设计

本文讨论了DSP与低速器件接口时的软件解决办法，以及该办法所存在的问题，并提出了相应的硬件解决方案，它能很好地解决DSP与各种外部器件的接口问题。     

Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person’s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)—SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.     

Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband code division multiple access and an orthogonal frequency division multiplexing receiver using the same coarse-grained reconfigurable MONTIUM tile processor is discussed. Besides the baseband processing part of the receiver, the same reconfigurable processor has also been used to implement Viterbi and Turbo channel decoders.     

演化硬件及面向演化的VLSI可重构体系结构设计

演化硬件在环境适应性和可靠性设计上具有潜在的巨大优势。文章介绍了数字和模拟电路演化综合的原理和步骤，几类典型的演化硬件平台及其局限性，重点讨论了面向演化的VLSI可重构体系结构，最后提出了这一新兴研究领域面临的一些问题及解决方法。     

可重构非线性布尔函数利用率模型研究与硬件设计

为解决序列密码中非线性布尔函数(Non-Linear Boolean Function, NLBF)硬件资源利用率低的问题,该文对以查找表(Look-Up Table, LUT)为基本构件的利用率模型进行研究,并结合适配算法的前期处理结果确定影响硬件利用率的3个基本参数(LUT大小、单元规模和输入端口数目);在此基础上,以变量频次为约束实现NLBF的映射,完成非线性运算单元的设计,单元支持多路并行处理。在SMIC 180 nm下进行逻辑综合,并行度为32时,工作频率达到241 MHz,吞吐率为7.71 Gb/s;对不同NLBF进行利用率评估,利用率均达到91.14%以上,并且随着并行度增加,利用率不断增大。     

应用于格密码的可重构多通道数论变换硬件设计

针对不同格密码体制带来的数论变换参数多样性,以及数论变换的性能优化设计,该文提出一种基于随机存取存储器(RAM)的可重构多通道数论变换单元。在数论变换单元设计中,在按时间抽取的基础上改进多通道架构,并提出一种优化地址分配方法。最后基于Xilinx Artix-7现场可编程逻辑门阵列(FPGA)平台进行原型实现,结果显示,所设计的数论变换单元消耗的资源为1744 Slices, 16 DSP,完成1次多项式乘法的时间为2.01 μs(n=256), 3.57 μs(n=512), 6.71 μs(n=1024)和13.43 μs(n=2048),支持256～2048的不同参数n和13～32 bit模q的可重构配置,工作频率最高可达232 MHz。     

基于SytemC动态可重构系统硬件任务管理模型

采用基于框架的建模仿真方法,对动态可重构系统进行设计空间搜索,需要建立仿真模型评估任务的管理策略.为此,文中利用SystemC搭建了一种动态可重构系统的硬件任务管理模型,该模型可根据不同的管理策略和重构资源进行调整.仿真实验结果表明,通过模型仿真获得硬件任务,在指定管理策略和资源约束下的实时调度布局信息,并针对具体应用...