可配置的先进超低功耗逻辑解决方案

该系列器件由可配置逻辑门组成,这些逻辑门能够让单一双输入器件实现多项逻辑功能。74AUP系列能够实现多达9种不同的逻辑功能：与、与非、或、或非、异或、异或非、多路复用、反相器和缓冲器。     

磁耦合元胞自动机逻辑器件的形状可重配置结构

磁耦合元胞自动机逻辑器件(即纳磁体逻辑器件)是后CMOS时代的一种极具潜力的新技术,具有无引线集成、极低功耗和天然非易失性等优点.纳磁体逻辑器件由纳米级单畴磁体构成,而磁体的形状是其一个重要的器件特征参数.本文研究了不同特殊形状纳磁体的转换特性,获得了改变特殊形状器件状态的时钟场值.提出了基于不同尺寸特殊形状纳磁体的可重配置择多逻辑门,采用OOMMF软件验证了形状择多逻辑门的输入可重配置性,得到了顺序配置不同输入组合所需的时钟场.该可重配置门结构的提出为磁性可编程逻辑计算电路的实现奠定了重要的理论基础.     

美国国家半导体推出可配置的传感器模拟前端电路

美国国家半导体公司日前推出两款可配置的传感器模拟前端(AFE)集成电路,两款产品采用美国国家半导体的独创技术,并获得多款全新设计工具的支持,令系统设计工程师可以使用各大厂商生产的各类传感器产品完成信号路径设计,将产品快速推向     

飞兆半导体推出可配置的先进超低功耗逻辑解决方案

提供设计灵活性并简化采购和供应管理移动和便携领域的设计工程师面对两项挑战,一是必须减少特定设计的订购部件数目,以便简化供应管理,二是需要降低逻辑门的工作电压范围。为满足这些需求,（Fairchild）开发了通用的多功能可配置74AUP系列TinyLogic器件。     

飞兆推出可配置的超低功耗逻辑解决方案74AUP系列

移动和便携领域的设计工程师面对两项挑战,一是必须减少特定设计的订购组件数目,以便简化供应管理,二是需要降低逻辑门的工作电压范围。为满足这些需求,飞兆半导体公司开发了通用的多功能可配置74AUP系列TinyLogic器件。     

手机用TFT彩色液晶显示驱动芯片的可配置接口电路设计

TFT彩色液晶显示驱动芯片的接口电路是手机主机与其显示驱动芯片之间数据通讯的桥梁.常用的接口类型主要有68、80和SPI三种,它们的动作时序与所用信号线各不相同.文章首先分析了这三种接口类型的读写时序,在此基础上提出了与这三种数据格式相兼容的可配置异步接口电路的设计方案,并给出相对应的验证结果及其在0.25μm CMOS工艺库下的综合结果.     

Configurable memristive logic block for memristive-based FPGA architectures

This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25 nW, and the memristive logic cells reduce device area by 60.416 µm². In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

Configurable array logic circuits for computing network error detection codes

Configurable Array Logic (CAL) has a basic architecture which is a cellular array with nearest neighbor connections. The cells in the array are dynamically programmable using transistor switches controlled by static RAM cells. Each cell can realize any two-input Boolean operation or act as a simple latch, as well as providing routing for pass-through connections to allow non-neighbor inter-cell connections. In this article, we demonstrate the versatility of the CAL technology by presenting efficient CAL circuits for computing all of the major error detection codes now in use for worldwide computer networking; these include CCITT, IEEE, Internet and ISO standard codes. The circuits, each having a version which comfortably fits on to a single 32×32 cell CAL chip, are appropriate for use as hardware accelerators to help computers deal with the ever increasing rates of data transmission over networks. The first class of error detection codes described are thecyclic redundancy codes (CRCs), which are in virtually universal use for bit serial transmission over physical links. The other class of error detection codes described are themodulo 2 ⁿ — 1checksums, which are in common use for byte transmission over networks and inter-networks.     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger circuit has been realised, using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger using only four MOS transistors is discussed. This circuit, which works on the principle of load-coupled regenerative feedback, can be implemented using conventional CMOS technology with only one extra fabrication step. It can be implemented even more easily in CMOS/SOS (silicon-on-sapphire) integrated circuits. The hysteresis of this Schmitt trigger can be controlled by a proper choice of the transistor geometries.     

Low power Schmitt trigger circuit

Three new Schmitt trigger circuits are described. The first circuit is a truly low power, while the second and third circuits are derived from the first circuit and provide smaller hysteresis width. Measurement results for the new Schmitt trigger circuits are presented. All the designed circuits are simulated using HSPICE with level 28 model parameters for a 1.2 μm standard CMOS technology. An application to the design of low power, very low frequency integrator oscillators is described     

A GaN/InGaN/AlGaN MQW RTD for versatile MVL applications with improved logic stability

To improve the logic stability of conventional multi-valued logic (MVL) circuits designed with a GaN-based resonate tunneling diode (RTD),we proposed a GaN/InGaN/AlGaN multi-quantum well (MQW) RTD.The proposed RTD was simulated through solving the coupled Schrodinger and Poisson equations in the numerical non-equilibrium Green's function (NEGF) method on the TCAD platform.The proposed RTD was grown layer by layer in epitaxial technologies.Simulated results indicate that its current-voltage characteristic appears to have a wider total negative differential resistance region than those of conventional ones and an obvious hysteresis loop at room temperature.To increase the Al composite of AlGaN barrier layers properly results in increasing of both the total negative differential resistance region width and the hysteresis loop width,which is helpful to improve the logic stability of MVL circuits.Moreover,the complement resonate tunneling transistor pair consisted of the proposed RTDs or the proposed RTD and enhanced mode HEMT controlled RTD is capable of generating versatile MVL modes at different supply voltages less than 3.3 V,which is very attractive for implementing more complex MVL function digital integrated circuits and systems with less devices,super high speed linear or nonlinear ADC and voltage sensors with a built-in super high speed ADC function.     

CoMM: Configurable Multimedia Middleware

1　Introduction　Multimediaservicesarebecomingincreasinglypopularincommunicationandinformationfields.Withthedistributedenvironment,multimediaap plicationsdeploymanyheterogeneousdevices .Also ,thetraditionalgeneral purposeoperatingsystems,likeWindowsandUNIX ,can tmeettherealtimerequirementofthemultimediadata,andarenotgoodatsupportingdistributedapplications.Tosolvetheseproblems,middlewarehasbeenimplementedformanyservicesinvariousforms.Thewebserviceisthenextimportantfieldtoimplementthemiddle w…     

Low voltage CMOS Schmitt trigger circuits

Two new low voltage Schmitt trigger circuits are presented which use a dynamic body-bias technique. The first circuit is designed for operation at 1 V. The second circuit, derived from the first circuit, is designed for operation at 0.4 V. Experimental results for the new Schmitt trigger circuits are presented.     

Schmitt trigger circuit with picosecond risetimes

A Schmitt trigger circuit is described which overcomes some of the stability problems associated with the wide hysteresis loop of more conventional arrangements. A low level of hysteresis is achieved, thereby reducing the threshold voltage while also affording increased stability during switching. Operational risetimes of 200 ps are demonstrated.