Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Novel back‐channel‐etch process flow based a‐IGZO TFTs for circuit and display applications on PEN foil

In this study, we report high‐quality amorphous indium–gallium–zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back‐channel‐etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0 cm²/(V·s), subthreshold slopes of 0.3 V/decade, and off‐currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 10⁴ s in both positive (+1.0 MV/cm) and negative (?1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19‐stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active‐matrix organic light‐emitting diode display.     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Highly reliable a‐IGZO TFTs on a plastic substrate for flexible AMOLED displays

We have successfully reduced threshold voltage shifts of amorphous In–Ga–Zn–O thin‐film transistors (a‐IGZO TFTs) on transparent polyimide films against bias‐temperature stress below 100 mV, which is equivalent to those on glass substrates. This high reliability was achieved by dense IGZO thin films and annealing temperature below 300 °C. We have reduced bulk defects of IGZO thin films and interface defects between gate insulator and IGZO thin film by optimizing deposition conditions of IGZO thin films and annealing conditions. Furthermore, a 3.0‐in. flexible active‐matrix organic light‐emitting diode was demonstrated with the highly reliable a‐IGZO TFT backplane on polyimide film. The polyimide film coating process is compatible with mass‐production lines. We believe that flexible organic light‐emitting diode displays can be mass produced using a‐IGZO TFT backplane on polyimide films.     

Instability dependent upon bias and temperature stress in amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors

Abstract— The effects of gate‐bias stress, drain‐bias stress, and temperature on the electrical parameters of amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors have been investigated. Results demonstrate that the devices suffer from threshold‐voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature‐assisted charging and discharging phenomenon of preexisting traps at the near‐interface and the a‐IGZO channel region. The experimental results show that applying a drain‐bias stress obviously impacts the instability of a‐IGZO TFTs; however, the instability caused by drain bias is not caused by hot‐electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.     

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V_T variation increases sharply as the channel length decreases because of the large resistance R_offset when it is formed at a‐IGZO source/drain. In the experiment, R_offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.     

High‐mobility self‐aligned top‐gate oxide TFT for high‐resolution AM‐OLED

High‐mobility and highly reliable self‐aligned top‐gate oxide thin‐film transistor (TFTs) were developed using the aluminum reaction method. Al diffusion to the oxide semiconductor and homogenization of the oxygen concentration in the depth direction after annealing were confirmed by laser‐assisted atom probe tomography. The high mobility of the top‐gate TFT with amorphous indium tin zinc oxide channel was demonstrated to be 32 cm²/V s. A 9.9‐in. diagonal qHD active‐matrix organic light‐emitting diode (AM‐OLED) display was fabricated using a five‐mask backplane process to demonstrate an applicable solution for large‐sized and high‐resolution AM‐OLEDs.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

Indium gallium zinc oxide (IGZO) is deposited using plasma‐enhanced spatial atomic layer deposition (sALD) on substrates as large as 32 × 35 cm². Excellent uniformity and thickness control leads to high‐performing and stable coplanar top‐gate self‐aligned (SA) thin‐film transistors (TFTs). The integration of a sALD‐deposited aluminum oxide buffer layer into the TFT stack further improves uniformity and stability. The results demonstrate the viability of atmospheric sALD as a novel deposition technique for the flat‐panel display industry.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Comparative study of a‐IGZO TFTs with direct current and radio frequency sputtered channel layers

In this work, a comparative study of electrical properties and gate‐bias stress stability between direct current (DC)‐sputtered and radio frequency (RF)‐sputtered amorphous indium–gallium–zinc oxide thin film transistors (a‐IGZO TFTs) is conducted. The RF‐sputtered a‐IGZO TFTs show higher field‐effect mobility and steeper sub‐threshold slope. The DC‐sputtered ones show a better uniformity of threshold voltage, enhanced stability under both positive bias stress and negative bias illumination stress. The X‐ray photoelectron spectroscopy characterization of the a‐IGZO films reveals that the concentration of oxygen vacancies and electron density in the RF‐sputtered a‐IGZO film is higher than that in the DC‐sputtered one, which probably accounts for the differences of electrical properties between the RF‐sputtered and DC‐sputtered a‐IGZO TFTs.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

We present a qHD (960 × 540 with three sub‐pixels) top‐emitting active‐matrix organic light‐emitting diode display with a 340‐ppi resolution using a self‐aligned IGZO thin‐film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven‐layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low‐temperature polycrystalline silicon. By using an IGZO thin‐film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low‐refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.     

Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 10¹¹ cm^?2/eV and Nss = 7.0×10¹⁶ cm^?3/eV for the unannealed TFT, which increased to 5.2×10¹¹ cm^?2/eV and 9.8×10¹⁶ cm^?3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×10¹¹ cm^?2/eV and Nss = 3.2×10¹⁶ cm^?3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.