Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

Novel back‐channel‐etch process flow based a‐IGZO TFTs for circuit and display applications on PEN foil

In this study, we report high‐quality amorphous indium–gallium–zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back‐channel‐etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0 cm²/(V·s), subthreshold slopes of 0.3 V/decade, and off‐currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 10⁴ s in both positive (+1.0 MV/cm) and negative (?1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19‐stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active‐matrix organic light‐emitting diode display.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.     

Impact of source/drain contacts formation of self‐aligned amorphous‐IGZO TFTs on their negative‐bias‐illumination‐stress stabilities

In this study, we have compared the performance of self‐aligned a‐IGZO thin‐film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiN_x interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field‐effect mobility (μ_FE) of over 10.0 cm²/(V.s), sub‐threshold slope (SS^‐1) of 0.5 V/decade, and current ratio (I_ON/I_OFF) over 10⁸. However, under negative‐bias‐illumination‐stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma‐treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel.     

Design of a low‐power‐consumption a‐IGZO TFT‐based Vcom driver circuit with long‐term reliability

Abstract— An amorphous‐InGaZnO (a‐IGZO) thin‐film transistor (TFT)‐based Vcom driver circuit that has long‐term reliability and can be integrated with the pixel array on a panel has been designed. Owing to the Vcom inversion, the power consumed by the proposed driving scheme is 40% less than that consumed by the conventional line‐inversion method. The high mobility (>10 cm²/V‐sec) of the a‐IGZO TFTs allows the integration of devices with small channel widths (<750 μm) and thus keeps the overall device size small, which is important for displays with narrow bezels. The lifetime of the Vcom driver is improved by AC driving (by clocking the n‐th and (n + 1)‐th frame with 20 and 0 V, respectively) of the buffer TFTs.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Effect on electrical performance of titanium co‐sputtered IZO active‐channel thin‐film transistor

We investigated the electrical performance of Ti–IZO active‐channel layer thin‐film transistors (TFTs) using a radio frequency (RF) magnetron co‐sputtering system to co‐sputter IZO and Ti targets. The samples were fabricated by changing the RF gun power of the IZO. The other parameters such as the RF gun power of the Ti target, oxygen partial pressure [O₂/(Ar + O₂)], and initial and process pressure of the chamber were unchanged. Unlike the sample sputtered only with IZO, the thin films of the Ti–IZO samples could control the oxygen vacancy because Ti reacts with the oxygen in the IZO. Therefore, Ti–IZO thin films can suppress the carrier concentration and thus have an effect on the electrical performance of TFTs.     

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Abstract— High‐performance and excellent‐uniformity thin‐film transistors (TFTs) having bottom‐gate structures are fabricated using an amorphous indium‐gallium‐zinc‐oxide (IGZO) film and an amorphous‐silicon dioxide film as the channel layer and the gate insulator layer, respectively. All of the 94 TFTs fabricated with an area 1 cm² show almost identical transfer characteristics: the average saturation mobility is 14.6 cm²/(V‐sec) with a small standard deviation of 0.11 cm²/(V‐sec). A five‐stage ring‐oscillator composed of these TFTs operates at 410 kHz at an input voltage of 18 V. Pixel‐driving circuits based on these TFTs are also fabricated with organic light‐emitting diodes (OLED) which are monolithically integrated on the same substrate. It is demonstrated that light emission from the OLED cells can be switched and modulated by a 120‐Hz ac signal input. Amorphous‐IGZO‐based TFTs are prominent candidates for building blocks of large‐area OLED‐display electronics.     

Characteristics of a‐IZO TFTs with high‐κ HfSiOx gate insulator annealed in various conditions

In this work, we investigate the enhanced performance of amorphous indium zinc oxides‐based thin film transistors with hafnium silicate (HfSiO_x) gate insulators. HfSiO_x gate insulators annealed at various conditions are deposited by cosputtering of hafnium oxide and Si. The structural properties of HfSiO_x are investigated using the atomic force microscopy, X‐ray diffraction, and x‐ray photoelectron spectroscopy (XPS). techniques. Furthermore, the electrical characteristics of HfSiO_x are analyzed to investigate the effect of annealing conditions. We obtain optimal results for thin film transistors with HfSiO_x gate insulators annealed for 1 h at 100 °C, with a saturation mobility of 1.2 cm²/V · s, threshold voltage of 2.2 V, on current/off current ratio of 2.0 × 10⁶, and an insulator surface roughness of 0.187 nm root mean square.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Interface and bulk effects for bias—light‐illumination instability in amorphous‐In—Ga—Zn—O thin‐film transistors

Abstract— Positive‐current‐bias (PB) instability and negative‐bias—light‐illumination (NBL) instability in amorphous‐In—Ga—Zn—O (a‐IGZO) thin‐film transistors (TFTs) have been examined. The channel‐ thickness dependence indicated that the Vth instability caused by the PB stress is primarily attributed to defects in the bulk a‐IGZO region for unannealed TFTs and to those in the channel—gate‐insulator interface for wet‐annealed TFTs. The interface and bulk defect densities (Dit and Nss, respectively) are Dit = 4.8 × 10¹¹ cm^?2/eV and Nss = 7.0×10¹⁶ cm^?3/eV for the unannealed TFT, which increased to 5.2×10¹¹ cm^?2/eV and 9.8×10¹⁶ cm^?3/eV, respectively, by the PB stress test. These are reduced significantly to Dit = 0.82×10¹¹ cm^?2/eV and Nss = 3.2×10¹⁶ cm^?3/eV for the wet‐annealed TFTs and are unchanged by the PB stress test. It was also found that the photo‐response of a‐IGZO TFTs begins at 2.3 eV of photon excitation, which corresponds to subgap states observed by photoemission spectroscopy. The origin of the NBL instability for the wet‐annealed TFTs is attributed to interface effects and considered to be a trap of holes at the channel‐gate—insulator interface where migration of the holes is enhanced by the electric field formed by the negative gate bias.     

Polynomials‐based summation inequalities and their applications to discrete‐time systems with time‐varying delays

This paper proposes a novel summation inequality, say a polynomials‐based summation inequality, which contains well‐known summation inequalities as special cases. By specially choosing slack matrices, polynomial functions, and an arbitrary vector, it reduces to Moon's inequality, a discrete‐time counterpart of Wirtinger‐based integral inequality, auxiliary function‐based summation inequalities employing the same‐order orthogonal polynomial functions. Thus, the proposed summation inequality is more general than other summation inequalities. Additionally, this paper derives the polynomials‐based summation inequality employing first‐order and second‐order orthogonal polynomial functions, which contributes to obtaining improved stability criteria for discrete‐time systems with time‐varying delays. Copyright © 2017 John Wiley & Sons, Ltd.     

Flexible active‐matrix OLED displays: Challenges and progress

Abstract— Organic light‐emitting‐device (OLED) devices are very promising candidates for flexible‐display applications because of their organic thin‐film configuration and excellent optical and video performance. Recent progress of flexible‐OLED technologies for high‐performance full‐color active‐matrix OLED (AMOLED) displays will be presented and future challenges will be discussed. Specific focus is placed on technology components, including high‐efficiency phosphorescent OLED technology, substrates and backplanes for flexible displays, transparent compound cathode technology, conformal packaging, and the flexibility testing of these devices. Finally, the latest prototype in collaboration with LG. Phillips LCD, a flexible 4‐in. QVGA full‐color AMOLED built on amorphous‐silicon backplane, will be described.     

Stability analysis for T–S fuzzy systems with interval time‐varying delays and nonlinear perturbations

This paper is concerned with the problem of the robust stability for T–S fuzzy systems with interval time‐varying delay and nonlinear perturbations. The key features of the approach include the introduction of uncorrelated augmented matrix items into the Lyapunov functional and the use of some appropriate integral inequalities. Unlike the existing methodologies, the proposed approach involves neither free weighting matrices nor any model transformation. It can, however, lead to much less conservative stability criteria than the existing ones for the systems under consideration. The cases of perturbations are assumed to both nonlinear time‐varying perturbations and time‐varying uncertainties in linear fractional form. Numerical examples show that the obtained results are less conservative than the existing ones in the literature. Copyright © 2009 John Wiley & Sons, Ltd.     

Bounded consensus tracking for sampled‐data second‐order multi‐agent systems with fixed and Markovian switching topology

This paper studies the bounded consensus tracking problems of second‐order multi‐agent systems with fixed and Markovian switching topology in a sampling setting. It is assumed that all the agents can only obtain the approximative value of the leader's acceleration instead of the actual value. Moreover, only a portion of agents can have the access to the leader and obtain the leader's position and velocity directly. By virtue of matrix analysis and perturbation theory, we present necessary and sufficient conditions for boundedness of tracking error system and show the ultimate bound of tracking errors under fixed and Markovian switching topology, respectively. Finally, a simulation example is given to illustrate the effectiveness of the results. Copyright © 2013 John Wiley & Sons, Ltd.