锁相鉴频器的噪声门限

本文论述了普通鉴频器的鉴频特性、噪声门限值产生的原因 ,并由此导出锁相环路鉴频器的原理及噪声门限 ,锁相环路鉴频器的优越性。     

具有锁相式频率合成器的跳频通信系统中的混沌

本文研究以锁相式频率合成器为核心构成的跳频通信系统中的混沌现象,分析了混沌对跳频通信系统的影响;利用Mel'nikov 方法证明了当系统参数满足一定条件时,系统输出混沌,并导出了系统出现混沌时与系统参数之间的关系;实验结果与理论分析相吻合.     

锁相鉴频器的门限研究

本文主要是研究有关门限范围方面的二阶锁相环路,其环路滤波器选择为(1/1 тS)或(1 т_1S/1 тS),也给出一阶环路的结果。研究了环路参数、失谐误差和调制的影响。可以看出,具有滤波器(1 т_1S/1 тS)的环路可用相同的带宽和阻尼的两种方法来构成。一个环路比另一个给出较好的阴限。分析的结果被计算机模拟和用环路的硬件模拟所得的试验工作证实。     

电视机中比例鉴频器的研究

介绍了电视机中对称式比例鉴频器的作用，电路的构成。利用矢量法论述了将调频波（6．5MHz的第二伴音中频信号）变为调相调幅波和对调相调幅波进行检波得到原调制信号（伴音信号）的工作原理。     

一种改进的混沌掩盖技术

该文分析了目前混沌掩盖系统存在的问题,产生的原因并提出了改进的方案。通过理论分析和计算机仿真,证明了改进方案真正实现了混沌掩盖通信。与原型系统对比,改进方案同时改善了系统的性能。     

DC-DC Boost变换器混沌现象研究

以DC—DC Boost变换器为例,理论分析,依据状态方程建立仿真模型,通过Matlab仿真,揭示了不同参数下的动力学行为特征,考察其通向混沌的道路,并对仿真结果进行了分析。     

Boost变换器混沌现象研究

电流控制型Boost变换器是电力电子系统中非线性现象研究的一个重要对象,具有规则的倍周期分岔结构,它能产生多种分岔形式,切分岔是其中的一种特殊分岔。     

基于混沌时间序列建模的频谱状态持续时长预测

为提高频谱利用率,该文利用非线性动力学理论对频谱状态持续时长序列进行建模并预测。以实际采集的频谱数据作为研究对象,采用指向导数法对该时长序列进行非一致延长时间相空间重构,利用基于尺度的Lyapunov指数判定其混沌特性。以基于Davidon-Fletcher-Powell方法的二阶Volterra预测模型 (DFPSOVF)为基础,提出一种基于限域拟牛顿方法的Volterra自适应滤波器系数调整模型,并将该模型应用于具有混沌特性的短时频谱状态持续时长预测,通过自适应剔除对预测贡献小的滤波器系数,降低预测模型的复杂度。实验结果表明该算法在保证预测精度的同时降低运算复杂度。     

DC-DC变换器中的混沌现象研究

本章将通过理论分析,建立其Simulink模型,研究DC—DC变换器在不同参数下的动力学行为特征,考察其通向混沌的道路,并对混沌现象进行仿真及分析。     

快速锁相无源三阶环路滤波器的设计与检测

在无源三阶环路滤波器的基础上,除了增加环路滤波器的环路带宽和降低相位裕量的参数以外,还可以通过增加硬件电路来提高环路的锁相速度;并提出了3种方法来检测锁相时间.     

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.     

使用GaAs MMIC技术的X波段微波频率检测器

The design, fabrication, and experimental results of an MEMS microwave frequency detector are presented for the first time. The structure consists of a microwave power divider, two CPW transmission lines, a microwave power combiner, an MEMS capacitive power sensor and a thermopile. The detector has been designed and fabricated on GaAs substrate using the MMIC process at the X-band successfully. The MEMS capacitive power sensor is used for detecting the high power signal, while the thermopile is used for detecting the low power signal. Signals of 17 and 10 dBm are measured over the X-band. The sensitivity is 0.56 MHz/fF under 17 dBm by the capacitive power sensor, and 6.67 MHz / μV under 10 dBm by the thermopile, respectively. The validity of the presented design has been confirmed by the experiment.     

Microwave frequency detector at X-band using GaAs MMIC technology

The design,fabrication,and experimental results of an MEMS microwave frequency detector are presented for the first time.The structure consists of a microwave power divider,two CPW transmission lines,a microwave power combiner,an MEMS capacitive power sensor and a thermopile.The detector has been designed and fabricated on GaAs substrate using the MMIC process at the X-band successfully.The MEMS capacitive power sensor is used for detecting the high power signal,while the thermopile is used for detecting the low power signal.Signals of 17 and 10 dBm are measured over the X-band.The sensitivity is 0.56 MHz/fF under 17 dBm by the capacitive power sensor,and 6.67 MHz//μV under 10 dBm by the thermopile.respectively.The validity of the presented design has been confirmed by the experiment.     

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks.     

锯齿形取样鉴相频率合成器混沌现象的研究

本文研究了锯齿形取样鉴相频率合成器环的混沌现象，通过验证原系统模型的相应降价系统存在快返反射点（snapnack repeller) ,从而证明了原系统有混沌输出。并给出了混沌的系统参数间的关系系。     

组合跳变随机平移宽间隔混沌跳频序列设计

为进一步提高宽间隔跳频序列的性能,基于混沌跳频序列,针对随机平移替代法存在的“窄点”平移与序列平衡性的矛盾问题,提出了一种新的组合跳变随机平移法。该方法在随机平移替代法的基础上取消“窄点”修正,引入组合跳变序列控制频点宽间隔映射。为兼顾组合跳变随机平移法产生序列的平衡性、汉明自相关性和宽间隔特性,构造了跳频序列的复合目标优化函数,引入粒子群算法计算得到最优的序列控制参数。仿真结果表明,组合跳变随机平移法可构造更多的序列,且产生的宽间隔混沌跳频序列具有更好的平衡性、汉明相关性和复杂度,采用粒子群优化获取的控制参数可以实现序列性能的均衡最优。     

Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

改进型鉴频鉴相器及电荷泵电路的设计*

本文设计了基于电荷泵架构锁相环电路的两个关键模块—鉴频鉴相器和改进型电流引导电荷泵。基于对扩展鉴相范围和消除死区方法的研究,鉴频鉴相器的性能得以优化。同时,为了保证电荷泵在一个宽输出电压范围内获得良好的电流匹配和较小的电流变化,许多额外的子电路被应用在电路设计中来改进电荷泵的架构。电路采用了标准90 nm CMOS 工艺设计实现并进行测试。鉴频鉴相器鉴相范围的测试结果为-354～354度,改进型电荷泵在0.2～1.1 V的输出电压范围内的电流失配比小于1.1%,泵电流变化小于4%。电路在1.2 V供电电压下的动态功耗为1.3mW。     

应用锁相环技术判别混沌相变的方法

针对经典的李氏指数法(Lyapunov Exponential Method)等混沌相变判别方法复杂度高的问题,提出了一种应用锁相环技术判别混沌相变的新方法.首先,理论推导了混沌系统的解析特性,分析了系统在不同相态下含有的频率成分;然后,构建了针对混沌系统的数字锁相环模型,研究锁相环下混沌态和大周期态呈现的频率特性;最后,提出了一种基于锁相环技术的混沌相变判别新方法.仿真实验显示,相比于李氏指数法,所提方法判别速度快一个数量级,检测差错率为0时,性能提高近2 dB.新方法应用锁相环技术,简便易行,判别速度快,为混沌相变判别的工程应用提供了新的手段.