首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 15 毫秒
1.
In this paper a new approach to fragile watermarking technique is introduced. This problem is particularly interesting in the field of modern multimedia applications, when image and video authentication are required. The approach exploits the cellular automata suitability to work as pseudorandom pattern generators and extends the related algorithms under the framework of the cellular non‐linear networks (CNNs). The result is a novel way to perform watermarking generation in real time, using the presently available CNN‐universal chip prototypes. In this paper, both the CNN algorithms for fragile watermarking as well as on‐chip experimental results are reported, confirming the suitability of CNNs to successfully act as real‐time watermarking generators. The availability of CNN‐based visual microprocessors allows to have powerful algorithms to watermark in real time images or videos for efficient smart camera applications. Copyright © 2004 John Wiley & Sons, Ltd.  相似文献   

2.
We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.  相似文献   

3.
This paper overviews some massively parallel topographic cellular computational approaches proposed for contour localization and tracking. When implemented on a focal plane cellular array microprocessor, these algorithms offer real‐time object contour localization and tracking—even at very high frame rates. Three specific methods (Constrained Wave Computing, Pixel Level Snakes and Moving Patch Method) will be described and compared along with their associated hardware–software architectures. Computational complexity, implementation, and performance related issues are discussed on a common platform (ACE‐BOX with the ACEx CNN‐UM chips). In conclusion, a novel architecture is proposed incorporating the best solutions learned from this comparative study. Copyright © 2006 John Wiley & Sons, Ltd.  相似文献   

4.
Biologically inspired control of artificial locomotion often makes use of the concept of central pattern generator (CPG), a network of neurons establishing the locomotion pattern within a lattice of neural activity. In this paper a new approach, based on cellular neural networks (CNNs), for the design of CPGs is presented. From a biological point of view this new approach includes an approximated chemical synapse realized and implemented in a CNN structure. This allows to extend the results, previously obtained with a reaction‐diffusion‐CNN (RD‐CNN) for the locomotion control of a hexapod robot, to a more general class of artificial CPGs in which the desired locomotion pattern and the switching among patterns are realized by means of a spatio‐temporal algorithm implemented in the same CNN structure. Copyright © 2002 John Wiley & Sons, Ltd.  相似文献   

5.
This work falls into the category of linear cellular neural network (CNN) implementations. We detail the first investigative attempt on the CMOS analog VLSI implementation of a recently proposed network formalism, which introduces time‐derivative ‘diffusion’ between CNN cells for nonseparable spatiotemporal filtering applications—the temporal‐derivative CNNs (TDCNNs). The reported circuit consists of an array of Gm‐C filters arranged in a regular pattern across space. We show that the state–space coupling between the Gm‐C‐based array elements realizes stable and linear first‐order (temporal) TDCNN dynamics. The implementation is based on linearized operational transconductance amplifiers and Class‐AB current mirrors. Measured results from the investigative prototype chip that confirms the stability and linearity of the realized TDCNN are provided. The prototype chip has been built in the AMS 0.35 µm CMOS technology and occupies a total area of 12.6 mm sq, while consuming 1.2 µW per processing cell. Copyright © 2010 John Wiley & Sons, Ltd.  相似文献   

6.
The paper considers a feedback cellular neural network (CNN) obtained by interconnecting elementary cells with an ideal capacitor and an ideal flux‐controlled memristor. It is supposed that during the analogue computation of the CNN the memristors behave as dynamic elements, so that each dynamic memristor (DM)‐CNN cell is described by a second‐order differential system in the state variables given by the capacitor voltage and the memristor flux. The proposed networks are called DM‐CNNs, that is CNNs using a dynamic (D) memristor (M). After giving a foundation to the DM‐CNN model, the paper establishes a fundamental result on complete stability, that is convergence of solutions toward equilibrium points, when the DM‐CNN has symmetric interconnections. Because of the presence of dynamic memristors, a DM‐CNN displays peculiar and basically different dynamic properties with respect to standard CNNs. First of all a DM‐CNN computes during the time evolution of the memristor fluxes, instead of the capacitor voltages as for a standard CNN. Furthermore, when a steady state is reached, the memristors keep in memory the result of the computation, that is the limiting values of the fluxes, while all memristor currents and voltages, as well as all currents, voltages, and power in the DM‐CNN vanish. Instead, for standard CNNs, currents, voltages, and power do not drop off when a steady state is reached. Copyright © 2016 John Wiley & Sons, Ltd.  相似文献   

7.
We propose a novel paradigm for cellular neural networks (CNNs), which enables the user to simultaneously calculate up to four subband images and to implement the integrated wavelet decomposition and a subsequent function into a single CNN. Two sets of experiments were designated to test the performance of the paradigm. In the first set of experiments, the effects of seven different wavelet filters and five feature extractors were studied in the extraction of critical features from the down‐sampled low‐low subband image using the paradigm. Among them, the combination of DB53 wavelet filter and the r=2 halftoning processor was determined to be most appropriate for low‐resolution applications. The second set of experiments demonstrated the capacity of the paradigm in the extraction of features from multi‐subband images. CNN edge detectors were embedded in a two‐subband digital wavelet transformation processor to extract the horizontal and vertical line features from the LH and HL subband images, respectively. A CNN logic OR operator proceeds to combine the results from the two subband line‐edge detectors. The proposed edge detector is capable of delineating more subtle details than using typical CNN edge detector alone, and is more robust in dealing with low‐contrast images than traditional edge detectors. The results demonstrate the proposed paradigm as a powerful and efficient scheme for image processing using CNN. Copyright © 2008 John Wiley & Sons, Ltd.  相似文献   

8.
In this paper, a vertebrate retina model is described based on a cellular neural network (CNN) architecture. Though largely built on the experience of previous studies, the CNN computational framework is considerably simplified: first‐order RC cells are used with space‐invariant nearest‐neighbour interactions only. All non‐linear synaptic connections are monotonic continuous functions of the pre‐synaptic voltage. Time delays in the interactions are continuous represented by additional first‐order cells. The modelling approach is neuromorphic in its spirit relying on both morphological and pharmacological information. However, the primary motivation lies in fitting the spatio‐temporal output of the model to the data recorded from biological cells (tiger salamander). In order to meet a low‐complexity (VLSI) implementation framework some structural simplifications have been made. Large‐neighbourhood interaction (neurons with large processes), furthermore inter‐layer signal propagation are modelled through diffusion and wave phenomena. This work presents novel CNN models for the outer and some partial models for the inner (light adapted) retina. It describes an approach that focuses on efficient parameter tuning and also makes it possible to discuss adaptation, sensitivity and robustness issues on retinal ‘image processing’ from an engineering point of view. Copyright © 2001 John Wiley & Sons, Ltd.  相似文献   

9.
In this paper, we propose and implement a 12‐bit area‐efficient folded all‐digital maximum power point tracking (MPPT) chip based on gain‐adaptive perturb‐and‐observe algorithm for photovoltaic energy conversion system. Alternative to DSP or micro controller, realizing the MPPT algorithm by using ASIC can achieve higher energy conversion efficiency, lower power consumption and smaller chip area. By using gain‐adaptive perturb‐and‐observe MPPT algorithm, overall system power consumption can be reduced by overcoming the periodic perturbation issues that occur in conventional perturb‐and‐observe MPPT algorithm. The utilization of proportional integral controller allows fast and stable tracking of the maximum power point. Under high intensity sun illumination, the gain‐adaptive perturb‐and‐observe algorithm performs three times faster than the conventional perturb‐and‐observe MPPT algorithm. Under low intensity sun illumination, the gain‐adaptive perturb‐and‐observe algorithm can provide the same power conversion efficiency as the conventional perturb‐and‐observe MPPT algorithm. By using folding VLSI architecture, the MPPT algorithm can be realized with 74% chip area saving and 77% power consumption reduction. Finally, our proposed MPPT chip is implemented in TSMC0.18‐µm process, with 0.85 mm*0.79 mm chip area and 97.9% power conversion efficiency. Copyright © 2013 John Wiley & Sons, Ltd.  相似文献   

10.
A new methodology for real-time processing of DNA chip images is proposed. The idea developed here is to use the cellular neural network (CNN) array to analyze the DNA microarray. A CNN is an analog dynamic processor array that reflects this property: the processing elements interact directly within a finite local neighborhood. Due to its architecture, a two-dimensional CNN array is widely used to solve image processing and pattern recognition problems; moreover, the parallelism characteristic of this structure allows one to perform the most computationally expensive image analysis tasks three orders of magnitude faster than a classical CPU-based computer. This approach, thanks to the supercomputing capabilities of the CNN architecture, makes the whole DNA chip methodology fully parallel and also makes the processing phase, until now very time consuming, a real-time step. We discuss the results of testing an algorithm based on the CNN universal machine (CNN-UM) that has been designed to classify the image data. The algorithm is implemented in an analogic (analog and logic) microprocessor.  相似文献   

11.
A high speed target detection and tracking algorithm for a CNN‐UM chip is presented in this paper. The target confidence value is computed based on the fusion of target existence probabilities of features using products of weighted sums. The target decision is done with such a confidence value and target initiation is done through the temporal accumulation of the confidence. The probability of the target existence for each feature is created in the region of influence depending on the reliability and the strength of the feature. By virtue of the analogic parallel processing structure of the CNN‐UM (Roska T, Chua LO. The CNN universal machine: an analogic array computer. IEEE Trans. Circuits Systems II 1993; CAS‐40 : 163–173), real time tracking can be achieved with presently available technologies with the speed of several kilo‐frames per second. Due to the utilization of multiple features of target, robust target detection is possible via the proposed algorithm. On‐chip experiments of the proposed target‐tracking algorithm have been done and properties of the proposed approach are disclosed through the various experiments. Copyright © 2003 John Wiley & Sons, Ltd.  相似文献   

12.
This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd.  相似文献   

13.
This paper presents a new CNN‐based architecture for real‐time video coding applications. The proposed approach, by exploiting object‐oriented CNN algorithms and MPEG encoding capabilities, enables low bit‐rate encoder/decoder to be designed. Simulation results using Claire video sequence show the effectiveness of the proposed scheme. Copyright © 2005 John Wiley & Sons, Ltd.  相似文献   

14.
Clock distribution networks consume a significant amount of the whole chip power budget. Therefore, reduction in the power consumption of the clock networks is a significant objective in high‐performance Integrated Circuit (IC) designs. This paper presents a novel Particle Distance Weighted Clustering (PDWC)‐Unity Clustering Optimization (UCO) algorithm for the placement of clock buffers in the Field Programmable Gate Array (FPGA) architecture. A novel PDWC algorithm is applied for clustering the logical components based on the minimum distance between components. A UCO algorithm is developed to determine the location for the placement of the buffers. This clustering technique reduces the delay rate of the architecture because of the minimum number of logical components. The overall area and power consumption of the FPGA architecture are reduced because of the placement of the buffers and latches. Our proposed PDWC‐UCO algorithm achieves lower delay, power consumption, wire length, latency and skew than the existing Flip‐Flop (FF) merging and register clustering algorithms. Copyright © 2016 John Wiley & Sons, Ltd.  相似文献   

15.
We show how cellular neural networks (CNNs) are capable of providing the necessary signal processing needed for visual navigation of an autonomous mobile robot. In this way, even complex feature detection and object recognition can be obtained in real time by analogue hardware, making fully autonomous real‐time operation feasible. An autonomous robot was first simulated and then implemented by simulating the CNN with a DSP. The robot is capable of navigating in a maze following lines painted on the floor. Images are processed entirely by a CNN‐based algorithm, and navigation is controlled by a fuzzy‐rule‐based algorithm. Copyright © 2002 John Wiley & Sons, Ltd.  相似文献   

16.
17.
Nonlinear equalisers based on minimum BER are proposed for the equalisation of nonlinear time‐varying channels. To train the equalisers online, a sliding‐window‐based hybrid quasi‐Newton algorithm is proposed. Switching between sliding‐window stochastic gradient algorithm and sliding‐window quasi‐Newton algorithm makes the new algorithm significantly stabler with a fast convergence rate. Results from extensive simulation tests show that performance of nonlinear equalisers based on minimum BER is better than the equaliser based on minimum mean square error. The proposed algorithm demonstrates high efficiency as well. Copyright © 2013 John Wiley & Sons, Ltd.  相似文献   

18.
This paper presents a 16‐channel power‐efficient neural/muscular stimulation integrated circuit for peripheral nerve prosthesis. First, the theoretical analysis is presented to show the power efficiency optimization in a stimulator. Moreover, a continuous‐time, biphasic exponential‐current‐waveform generation circuit is designed based on Taylor series approximation and implemented in the proposed stimulation chip to optimize the power efficiency. In the 16‐channel stimulator chip design, each channel of the stimulator consists of a current copier, an exponential current generator, an active charge‐balancing circuit, and a 24‐V output stage. Stimulation amplitude, pulse width, and frequency can be set and adjusted through an external field‐programmable gate array by sending serial commands. Finally, the proposed stimulator chip has been fabricated in a 0.18‐μm advanced complementary metal‐oxide‐semiconductor process with 24‐V laterally diffused metal oxide semiconductor option. The maximum stimulation power efficiency of 95.9% is achieved at the output stage with an electrode model of 10‐kΩ resistance and 100‐nF capacitance. Animal experiment results further demonstrate the power efficiency improvement and effectiveness of the stimulator.  相似文献   

19.
This paper presents image thinning algorithms using cellular neural networks (CNNs) with one‐ or two‐dimensional opposite‐sign templates (OSTs) as well as non‐unity gain output functions. Two four‐layer CNN systems with one‐dimensional (1‐D) OSTs are proposed for image thinning with 4‐ or 8‐connectivity, respectively. A CNN system, which consists of an eight‐layer CNN with two‐dimensional (2‐D) OSTs followed by another four‐layer CNN with 2‐D OSTs, is constructed for image thinning with 8‐connectivity, in which designs of B‐ and I‐templates are simpler than in CNNs with 1‐D OSTs. In the aforementioned designs, parameter values of 1‐D OSTs are chosen to make CNNs operate with thinning‐like property 1 (TL‐1), and those of 2‐D OSTs with 2‐D thinning‐like property (2‐DTL). Simulation studies show that these CNN systems have a good image thinning performance. Copyright © 1999 John Wiley & Sons, Ltd.  相似文献   

20.
An analogic CNN algorithm is proposed for detection of multiple moving objects in high resolution, grey‐scale images taken from a fixed camera. The algorithm, based on simple 3 × 3 templates, can be implemented using CNN hardware, providing the real‐time operation required in surveillance and traffic control applications. Efficient separation of moving objects from the background is obtained through automatic threshold selection. The performance of the proposed method is shown using real‐life indoor and outdoor video sequences. Copyright © 2004 John Wiley & Sons, Ltd.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号