An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

Uniform approximation of time‐invariant non‐linear systems

An Erratum has been published for this article in International Journal of Circuit Theory and Applications 2004; 32(6):633. It is shown that the elements of a large class of time‐invariant non‐linear input–output maps can be uniformly approximated arbitrarily well, over infinite time intervals, using a certain structure that can be implemented in many ways using, for example, radial basis functions, polynomial functions, piecewise linear functions, sigmoids, or combinations of these functions. For the special case in which these functions are taken to be certain polynomial functions, the input–output map of our structure is a generalized finite Volterra series. Results are given for the case in which inputs and outputs are defined on ?. The case in which inputs and outputs are defined on the half‐line ?₊ is also addressed, and in both cases inputs need not be functions that are continuous. Copyright © 2004 John Wiley & Sons, Ltd.     

A new adaptive multi‐bias S‐parameter measurement algorithm for transistor characterization

A new adaptive measurement algorithm is described for the control of an automated S‐parameter measurement set‐up used to characterize transistors for non‐linear modelling. The procedure differs from previous algorithms in that is uses both the device DC‐ and S‐parameter data to identify DC bias regions where the device characteristics are changing rapidly. By placing more bias points in these areas and less data points in regions where the device response stays constant, the non‐linear behaviour of the device can be characterized more accurately while keeping the total volume of the experimental data and hence the measurement time to an acceptable level. Experimental results are presented that illustrates the operation of the adaptive algorithm as well as the influence that the selection procedure has on non‐linear modelling results. Copyright © 2005 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Piecewise linear second moment statistical simulation of ICs affected by non‐linear statistical effects

This paper presents a methodology for statistical simulation of non‐linear integrated circuits affected by device mismatch. This simulation technique is aimed at helping designers maximize yield, since it can be orders of magnitude faster than other readily available methods, e.g. Monte Carlo. Statistical analysis is performed by modeling the electrical effects of tolerances by means of stochastic current or voltage sources, which depend on both device geometry and position across the die. They alter the behavior of both linear and non‐linear components according to stochastic device models, which reflect the statistical properties of circuit devices up to the second order (i.e. covariance functions). DC, AC, and transient analyses are performed by means of the stochastic modified nodal analysis, using a piecewise linear stochastic technique with respect to the stochastic sources, around a few automatically selected points. Several experimental results on significant circuits, encompassing both the analog and the digital domains, prove the effectiveness of the proposed method. Copyright © 2009 John Wiley & Sons, Ltd.     

An empirical I‐V model of tunneling real‐space transfer transistors for monostable–bistable transition logic element application

We proposed an empirical I‐V model to represent the negative differential resistance (NDR) regime of fabricated tunneling real‐space transfer transistors (TRSTTs). For TRSTTs to have great potential in monostable–bistable transition logic element (MOBILE) design, our model is able to accurately reproduce the NDR regime including gate‐source‐bias‐controlled NDR values and modulated peak to valley drain current ratios. The modeled I‐V curves, tranconductances, and NDRs with multiple gate biases are in good agreement with measured data. The key parameters in the model have clear physical meanings, and the value of these parameters is easy to be extracted directly from the test I‐V curves. The model is used to simulate a practical MOBILE, and excellent agreement between the simulated and measured data was found. Copyright © 2015 John Wiley & Sons, Ltd.     

Two‐dimensional non‐stationary numerical model for MSM structures

In this paper the solution of the non‐stationary model for MSM structures is obtained numerically. The two‐dimensional model consists of three singularly perturbed non‐linear partial differential equations. The alternating‐direction method for discretization in time and the non‐oscillatory streamline upwind method on a piecewise uniform grid for discretization in space are used to eliminate the interior and boundary layer oscillations. The described model is used for the analysis of the time response of a GaAs n‐type MSM structure to a Heaviside function form of the applied voltage. For the stationary case the I–V characteristic of the structure is determined. The numerical results confirm that the applied method is convenient for solving convection–diffusion problems. Copyright © 1999 John Wiley & Sons, Ltd.     

A systematic method for the development of a three‐phase transformer non‐linear model

In this work, a novel three‐phase transformer non‐linear model is developed. The proposed model takes into account the magnetic core topology and the windings connections. The non‐linear characteristic curve of the core material is introduced by its magnetization curve or by its hysteresis loop using the mathematical hysteresis model proposed by Tellinen or the macroscopic hysteresis model proposed by Jiles–Atherton. The eddy currents effects are included through non‐linear resistors using Bertotti's work. The proposed model presents several advantages. An incremental linear circuit, having the same topology with the magnetic circuit of the core, is used in order to directly write the differential equations of the magnetic part of the transformer. The matrix L _d that describes the coupling between the windings of the transformer is systematically derived. The electrical equations of the transformer can be easily written for any possible connection of the primary and secondary windings using the unconnected windings equations and transformation matrices. The proposed methods for the calculation of the coupling between the windings, the representation of the eddy currents and the inclusion of the core material characteristic curve can be used to develop a transformer model appropriate for the EMTP/ATP‐type programs. Copyright © 2009 John Wiley & Sons, Ltd.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Non‐linear performance comparison for FD and PD SOI MOSFETs based on the integral function method and Volterra modelling

The harmonic and intermodulation distortions of both fully‐depleted (FD) and partially‐depleted (PD) silicon‐on‐insulator (SOI) MOSFETs are studied. The analysis is based on the recently developed integral function method and the results are compared to a third‐order Volterra model of the MOSFET. This modelling helps us to understand the non‐linear mechanisms of the considered devices and to predict their frequency behaviour. The models are validated through large‐signal network analyser measurements. The devices performances are discussed. Copyright © 2005 John Wiley & Sons, Ltd.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel current conveyor‐based Schmitt trigger and its application as a relaxation oscillator

The current paper presents a novel Schmitt trigger using two second‐generation current conveyors and four resistors and its application as a relaxation oscillator. The performance of the proposed circuit is examined using Cadence and the model parameters of a 0.6µm CMOS process. The obtained results demonstrate excellent agreement with the theoretical values. The measured results based on commercially available current feedback operational amplifiers (AD 844 AN) are included and the non‐idealities are also examined. The topology reports low sensitivities and has features suitable for VLSI implementation. Copyright © 2010 John Wiley & Sons, Ltd.     

Adaptive least mean squares block Volterra filters

Adaptive filtering has found many applications in situations where the underlying signals are changing or unknown. While linear filters are simple from implementation and conceptual points of view, many signals are non‐linear in nature. Non‐linear filters based on truncated Volterra expansions can effectively model a large number of systems. Unfortunately, the resulting input auto‐moment matrix is ill conditioned, which results in a slow convergence rate. This paper proposes a class of block adaptive Volterra filters in which the input sequences are Hadamard transformed to improve the condition number of the input auto‐moment matrix and consequently improve the convergence rate. This is achieved by the decorrelation effect produced by the orthogonality of the transform. Since Hadamard transformation employs only ±1's, the additional required computational and implementation burdens are few. The effect of additive white Gaussian noise is introduced. Simulation experiments are given to illustrate the improved performance of the proposed method over the conventional Volterra LMS method. Copyright © 2001 John Wiley & Sons, Ltd.     

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

This paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (t_ox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_{C_AVG}, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (T_{C_AVG} = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_DD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.     

CMOS Non‐tailed differential pair

A continuous‐time complementary metal–oxide–semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common‐mode current is presented. Compared with a p‐channel long‐tailed pair, the proposed non‐tailed solution operates under a higher maximum input common‐mode voltage that includes (V_DD + V_SS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35‐µm technology (with metal – oxide – semiconductor thresholds greater than 0.6 V) confirm this behavior for supply voltages as low as 1.2 V, whereas the long‐tailed pair with the same technology offers the same capability only for supplies higher than 1.6 V. Copyright © 2015 John Wiley & Sons, Ltd.     

On the transposition of Gm–C filters to DC stabilized log‐domain filters

High‐order log‐domain filters could be designed by transposing the already known linear‐domain G_m–C filter topologies to the corresponding topologies in the log‐domain. This is achieved by using a non‐linear transconductor configuration, where the output current is exponentially related to its input and output voltages. A drawback of the non‐linear transconductor configuration already introduced in the literature is that a number of the transposed log‐domain filter topologies suffer from DC instability, while in some others a DC offset current appears at their output. In order to eliminate the aforementioned problems a modified non‐linear transconductor configuration for transposing G_m–C filter topologies to log‐domain filter topologies is introduced in this paper. The achieved improvements are demonstrated through a number of log‐domain filter configurations derived using the already introduced and the proposed transposition schemes. Copyright © 2006 John Wiley & Sons, Ltd.