Watermarking on CNN‐UM for image and video authentication

In this paper a new approach to fragile watermarking technique is introduced. This problem is particularly interesting in the field of modern multimedia applications, when image and video authentication are required. The approach exploits the cellular automata suitability to work as pseudorandom pattern generators and extends the related algorithms under the framework of the cellular non‐linear networks (CNNs). The result is a novel way to perform watermarking generation in real time, using the presently available CNN‐universal chip prototypes. In this paper, both the CNN algorithms for fragile watermarking as well as on‐chip experimental results are reported, confirming the suitability of CNNs to successfully act as real‐time watermarking generators. The availability of CNN‐based visual microprocessors allows to have powerful algorithms to watermark in real time images or videos for efficient smart camera applications. Copyright © 2004 John Wiley & Sons, Ltd.     

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

This paper presents a hardware design capable of supporting high‐efficiency video coding inverse discrete cosine transform (IDCT) with a 32×32 transform unit size, using a single 1‐D IDCT core with transpose memory to reduce costs. The proposed 1‐D IDCT core employs 16 computation paths for high throughput and is implemented using distributed arithmetic to facilitate the sharing of hardware resources. The proposed 1‐D IDCT is capable of calculating 1‐D and 2‐D data simultaneously along 32 parallel paths. When implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 40‐nm CMOS technology, the proposed 2‐D transform core provides throughput of 6.4 gigapixels/s with a gate count of 335 k. The results show that a superior hardware efficiency can be achieved in the proposed 32‐point IDCT core compared with the existing works. Copyright © 2017 John Wiley & Sons, Ltd.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

Improving Networks‐on‐Chip performability: A topology‐based approach

The performability metric is commonly used in Networks‐on‐Chip (NoC)‐based systems to represent their abilities to successfully complete specific tasks in finite time intervals. In this paper, we present a novel topology‐based performability model for NoC‐based systems. The model is used to evaluate the performability of NoC‐based systems at early design phases. A comparative study of nine commonly used network architectures is performed using the proposed model. The purpose of the study is to explore the impact of the network topology on the performability of NoC‐based systems. Using the output from this study, a new methodology is proposed to improve the performability of a given application at early design phases. In this methodology, a joint consideration of five design parameters (network topology, target application traffic distribution, mapping of processing elements, noise power, and voltage swing) is carried out. Using the proposed methodology, designers can select the optimal topology for a given application that maximizes system performability. The effectiveness of the proposed methodology in determining the optimal topology is verified by experimental work and validated through a case study of a video application. Copyright © 2010 John Wiley & Sons, Ltd.     

A method for the approximate synthesis of cellular non‐linear networks—Part 2: Circuit reduction

In this paper, we face the problem of model reduction in piecewise‐linear (PWL) approximations of non‐linear functions. The reduction procedure presented here is based on the PWL approximation method proposed in a companion paper and resorts to a strategy that exploits the orthonormality of basis functions in terms of a proper inner product. Such a procedure can be favourably applied to the synthesis of the resistive parts of cellular non‐linear networks (CNNs) to reduce the complexity of the resulting circuits. As an example, the method is applied to a case study concerning a CNN for image processing. Copyright © 2003 John Wiley & Sons, Ltd.     

Multi‐template approach to realize central pattern generators for artificial locomotion control

Biologically inspired control of artificial locomotion often makes use of the concept of central pattern generator (CPG), a network of neurons establishing the locomotion pattern within a lattice of neural activity. In this paper a new approach, based on cellular neural networks (CNNs), for the design of CPGs is presented. From a biological point of view this new approach includes an approximated chemical synapse realized and implemented in a CNN structure. This allows to extend the results, previously obtained with a reaction‐diffusion‐CNN (RD‐CNN) for the locomotion control of a hexapod robot, to a more general class of artificial CPGs in which the desired locomotion pattern and the switching among patterns are realized by means of a spatio‐temporal algorithm implemented in the same CNN structure. Copyright © 2002 John Wiley & Sons, Ltd.     

Preliminary results from an analog implementation of first‐order TDCNN dynamics

This work falls into the category of linear cellular neural network (CNN) implementations. We detail the first investigative attempt on the CMOS analog VLSI implementation of a recently proposed network formalism, which introduces time‐derivative ‘diffusion’ between CNN cells for nonseparable spatiotemporal filtering applications—the temporal‐derivative CNNs (TDCNNs). The reported circuit consists of an array of Gm‐C filters arranged in a regular pattern across space. We show that the state–space coupling between the Gm‐C‐based array elements realizes stable and linear first‐order (temporal) TDCNN dynamics. The implementation is based on linearized operational transconductance amplifiers and Class‐AB current mirrors. Measured results from the investigative prototype chip that confirms the stability and linearity of the realized TDCNN are provided. The prototype chip has been built in the AMS 0.35 µm CMOS technology and occupies a total area of 12.6 mm sq, while consuming 1.2 µW per processing cell. Copyright © 2010 John Wiley & Sons, Ltd.     

Cellular neural networks with opposite‐sign templates for image thinning

This paper presents image thinning algorithms using cellular neural networks (CNNs) with one‐ or two‐dimensional opposite‐sign templates (OSTs) as well as non‐unity gain output functions. Two four‐layer CNN systems with one‐dimensional (1‐D) OSTs are proposed for image thinning with 4‐ or 8‐connectivity, respectively. A CNN system, which consists of an eight‐layer CNN with two‐dimensional (2‐D) OSTs followed by another four‐layer CNN with 2‐D OSTs, is constructed for image thinning with 8‐connectivity, in which designs of B‐ and I‐templates are simpler than in CNNs with 1‐D OSTs. In the aforementioned designs, parameter values of 1‐D OSTs are chosen to make CNNs operate with thinning‐like property 1 (TL‐1), and those of 2‐D OSTs with 2‐D thinning‐like property (2‐DTL). Simulation studies show that these CNN systems have a good image thinning performance. Copyright © 1999 John Wiley & Sons, Ltd.     

Complete stability of feedback CNNs with dynamic memristors and second‐order cells

The paper considers a feedback cellular neural network (CNN) obtained by interconnecting elementary cells with an ideal capacitor and an ideal flux‐controlled memristor. It is supposed that during the analogue computation of the CNN the memristors behave as dynamic elements, so that each dynamic memristor (DM)‐CNN cell is described by a second‐order differential system in the state variables given by the capacitor voltage and the memristor flux. The proposed networks are called DM‐CNNs, that is CNNs using a dynamic (D) memristor (M). After giving a foundation to the DM‐CNN model, the paper establishes a fundamental result on complete stability, that is convergence of solutions toward equilibrium points, when the DM‐CNN has symmetric interconnections. Because of the presence of dynamic memristors, a DM‐CNN displays peculiar and basically different dynamic properties with respect to standard CNNs. First of all a DM‐CNN computes during the time evolution of the memristor fluxes, instead of the capacitor voltages as for a standard CNN. Furthermore, when a steady state is reached, the memristors keep in memory the result of the computation, that is the limiting values of the fluxes, while all memristor currents and voltages, as well as all currents, voltages, and power in the DM‐CNN vanish. Instead, for standard CNNs, currents, voltages, and power do not drop off when a steady state is reached. Copyright © 2016 John Wiley & Sons, Ltd.     

An efficient paradigm for wavelet‐based image processing using cellular neural networks

We propose a novel paradigm for cellular neural networks (CNNs), which enables the user to simultaneously calculate up to four subband images and to implement the integrated wavelet decomposition and a subsequent function into a single CNN. Two sets of experiments were designated to test the performance of the paradigm. In the first set of experiments, the effects of seven different wavelet filters and five feature extractors were studied in the extraction of critical features from the down‐sampled low‐low subband image using the paradigm. Among them, the combination of DB53 wavelet filter and the r=2 halftoning processor was determined to be most appropriate for low‐resolution applications. The second set of experiments demonstrated the capacity of the paradigm in the extraction of features from multi‐subband images. CNN edge detectors were embedded in a two‐subband digital wavelet transformation processor to extract the horizontal and vertical line features from the LH and HL subband images, respectively. A CNN logic OR operator proceeds to combine the results from the two subband line‐edge detectors. The proposed edge detector is capable of delineating more subtle details than using typical CNN edge detector alone, and is more robust in dealing with low‐contrast images than traditional edge detectors. The results demonstrate the proposed paradigm as a powerful and efficient scheme for image processing using CNN. Copyright © 2008 John Wiley & Sons, Ltd.     

Analogic CNN algorithm for estimating position and size of moving objects

An analogic CNN algorithm is proposed for detection of multiple moving objects in high resolution, grey‐scale images taken from a fixed camera. The algorithm, based on simple 3 × 3 templates, can be implemented using CNN hardware, providing the real‐time operation required in surveillance and traffic control applications. Efficient separation of moving objects from the background is obtained through automatic threshold selection. The performance of the proposed method is shown using real‐life indoor and outdoor video sequences. Copyright © 2004 John Wiley & Sons, Ltd.     

The network behind spatio‐temporal patterns: building low‐complexity retinal models in CNN based on morphology,pharmacology and physiology

In this paper, a vertebrate retina model is described based on a cellular neural network (CNN) architecture. Though largely built on the experience of previous studies, the CNN computational framework is considerably simplified: first‐order RC cells are used with space‐invariant nearest‐neighbour interactions only. All non‐linear synaptic connections are monotonic continuous functions of the pre‐synaptic voltage. Time delays in the interactions are continuous represented by additional first‐order cells. The modelling approach is neuromorphic in its spirit relying on both morphological and pharmacological information. However, the primary motivation lies in fitting the spatio‐temporal output of the model to the data recorded from biological cells (tiger salamander). In order to meet a low‐complexity (VLSI) implementation framework some structural simplifications have been made. Large‐neighbourhood interaction (neurons with large processes), furthermore inter‐layer signal propagation are modelled through diffusion and wave phenomena. This work presents novel CNN models for the outer and some partial models for the inner (light adapted) retina. It describes an approach that focuses on efficient parameter tuning and also makes it possible to discuss adaptation, sensitivity and robustness issues on retinal ‘image processing’ from an engineering point of view. Copyright © 2001 John Wiley & Sons, Ltd.     

A cellular non‐linear network for image fusion based on data regularization

In this paper, a synthesis method developed in the last few years is applied to derive a cellular non‐linear network (CNN) able to find an approximate solution to a variational image‐fusion problem. The functional to be minimized is based on regularization theory and takes into account two complementary principles, namely, knowledge source corroboration and belief enhancement/withdrawal, both typical of data‐fusion approaches. The obtained CNN has been tested by simulations (i.e. by numerically integrating the circuit state equations) in some case studies. The quality of the results is good, as turns out from comparisons with some standard methods. Copyright © 2006 John Wiley & Sons, Ltd.     

An oscillatory noise‐shaped quantizer for time‐based continuous‐time sigma‐delta modulators

In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.     

Automatic detection and tracking of moving image target with CNN‐UM via target probability fusion of multiple features

A high speed target detection and tracking algorithm for a CNN‐UM chip is presented in this paper. The target confidence value is computed based on the fusion of target existence probabilities of features using products of weighted sums. The target decision is done with such a confidence value and target initiation is done through the temporal accumulation of the confidence. The probability of the target existence for each feature is created in the region of influence depending on the reliability and the strength of the feature. By virtue of the analogic parallel processing structure of the CNN‐UM (Roska T, Chua LO. The CNN universal machine: an analogic array computer. IEEE Trans. Circuits Systems II 1993; CAS‐40 : 163–173), real time tracking can be achieved with presently available technologies with the speed of several kilo‐frames per second. Due to the utilization of multiple features of target, robust target detection is possible via the proposed algorithm. On‐chip experiments of the proposed target‐tracking algorithm have been done and properties of the proposed approach are disclosed through the various experiments. Copyright © 2003 John Wiley & Sons, Ltd.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

GRO‐TDC with gate‐switch‐based delay cell halving resolution limit

In this paper, we propose a time‐to‐digital converter (TDC) with first‐order noise‐shaping. The proposed gated ring oscillator (GRO)‐TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate‐switched configuration to solve the charge redistribution problem. The proposed GRO‐TDC is designed using a 65‐nm process technology, with an area of 0.015 mm² and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO‐TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO‐TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

Wide‐band dual‐resonance capacitive cross‐coupled divide‐by‐5 injection‐locked frequency divider

A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias V_DD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm².     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.