Application study of a high‐temperature superconducting fault current limiter for electric power system

Using high‐temperature superconductors, a superconducting fault current limiter (SFCL) was fabricated and tested. The superconductor and a vacuum interrupter serving as a commutation switch were connected in parallel with a bypass coil. When a fault occurs and excessive current flows, the superconductor is first quenched and the current is transferred to the bypass coil because of the voltage drop of the superconductor. At the same time, since a magnetic field is generated by the current flowing in the bypass coil, the commutation switch is immediately driven by an electromagnetic repulsion plate connected to the driving rod of the vacuum interrupter (VI), and the superconductor is separated from this circuit. Using the test model, we were able to separate the superconductor from the circuit by the movement of the VI within a half current cycle and to transfer all current to the bypass coil. Since the operation of the commutation switch is included in the current limiting operation of this test model, it will be a useful circuit in the development of SFCL in the future. Moreover, since it can make the energy consumption of the superconductor small during the fault state due to the realization of a high‐speed switch with simple composition, the burden on the superconductor is reduced compared with the conventional resistive type of SFCL and it is considered that the flexibility of SFCL design is increased. Cooperation with a circuit breaker was also considered; trial calculations of the parameters and energy of operation were conducted and a discussion of the installation of the SFCL in an electric power system is presented. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 155(4): 20–29, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20265     

Optimum design approach for low‐speed,high‐torque permanent magnet motors

This paper presents an optimum design approach for low‐speed, high‐torque permanent magnet motors. The approach is divided into two steps: the first consists of the rough estimation of torque by linear analysis, and the second the optimization of the motor configuration by nonlinear FEM analysis. Under restricted dimensional specifications and electrical requirements, a 16‐pole, 18‐coil permanent magnet motor with a rating of 600 Nm and 300 rpm was designed and constructed. © 2001 Scripta Technica, Electr Eng Jpn, 135(4): 52–63, 2001     

Proposal of current control method of high‐speed AC motor system

In this paper, a current control method for a high‐speed AC motor system is proposed. In high‐speed driving operation, the current controller tends to lose stability because of the dead time caused by computational delay and electromagnetic coupling included in the AC motor model. The main purpose of the proposed method is reduction of the dead time on the current controller. The proposed method is based on model predictive control and optimization of the start timing. The effectiveness of the proposed method is confirmed by simulation results. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(1): 37–45, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21083     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.     

From energy‐delay metrics to constraints on the design of digital circuits

In this paper, the adoption of general metrics of the energy‐delay tradeoff is investigated to achieve energy‐efficient design of digital CMOS very large‐scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of EⁱD^j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing EⁱD^j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65‐nm CMOS technology are also reported to exemplify the theoretical results. Copyright © 2011 John Wiley & Sons, Ltd.     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.     

A methodology to design continuous‐time adaptive equalizers

Serial communications systems suffer from channel bandwidth limitations that result in eye closure and inter‐symbol interference. Adaptive equalization at the receiver is widely implemented to alleviate this, and a number of continuous‐time techniques aiming multi‐gigabit operation have been proposed. The operation of adaptive equalizers is based on signal filtering carried out by loop filters whose characteristics are usually given ad‐hoc after a trial and error process. This paper presents a unified analysis of the operation of continuous‐time adaptive equalizers that results in a general design methodology to select the frequency characteristics of the filters implemented in the adaptation loop. Using the proposed methodology, a novel adaptation loop filter combination incorporating two low‐pass filters is presented. Copyright © 2016 John Wiley & Sons, Ltd.     

Analysis and design of voltage‐controlled current sources for a grounded load

The paper presents the structure and the principle of operation of the ‘improved’ Howland current pumps (or voltage‐controlled current sources (VCCSs) for a grounded load). In particular, under review is the VCCS employing power operational amplifier (op amp) and the VCCS using low power op amp and an additional power transistor, extending working dynamic range. On the basis of analysis of the operational principle, the equations for transfer functions of both circuits and formulas for the related dynamic electrical parameters are obtained. Moreover, using these formulas, a design procedure is developed, and recommendations for simulation modelling are given. The efficiency of the proposed procedure is verified by simulation modelling and experimental testing of sample electronic circuits of VCCSs. Copyright © 2013 John Wiley & Sons, Ltd.     

Visualization of high‐speed phenomena using an acousto‐optic laser deflector

An acousto‐optic laser deflector was used for visualization of high‐speed phenomena, such as shock waves and density perturbations accompanying an impulse discharge, or shock waves generated by laser‐induced breakdown in air. Using a continuous wave laser as the light source, shadowgraphs of shock waves and density perturbations were obtained at shutter speeds down to 1µs. Results showed that shock waves propagated at a speed of 417 m/s in the case of an impulse discharge, and 485 m/s in the case of laser‐induced breakdown. Prebreakdown phenomena such as leaders progressing from the high‐voltage electrode were also visualized. Compared to conventional high‐speed imaging techniques, this method is useful when using a laser light source, since the acousto‐optic crystal can accommodate high‐intensity laser light. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 154(3): 9–15, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20279     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis and design of a high‐compliance ultra‐high output resistance current mirror employing positive shunt feedback

This paper reports a novel high‐compliance, very accurate and ultra‐high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra‐high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post‐layout simulations. Designed in the IBM 130‐nm standard CMOS process, the circuit consumes 230 × 110 µm² of silicon area. Post‐layout simulation results indicate that with a 3.3‐V power supply, output voltage compliance of 0.93V_Supply is achieved at a maximum output current of 96 μA. Moreover, an extremely ultra‐high output resistance of 320 GΩ is achieved, which is one of the highest reported values of output resistance for current mirrors implemented using regular CMOS technology. The ?3 dB upper cut‐off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 μA to the load. Copyright © 2014 John Wiley & Sons, Ltd.     

Proposal of flux‐lock‐type fault current limiter with high‐TC superconducting element

This paper proposes a new type of fault current limiter (FCL), which consists of a high‐T_C superconducting (HTS) element and two coils wound on the same core without any leakage magnetic flux. In this FCL, either the limiting impedance or the initial limiting current level can be controlled by adjusting the inductances and the winding direction of the coils. Therefore, this FCL could relax the material restrictions on high‐T_C superconducting FCL. A current‐limiting experiment by a model FCL was carried out, and the limiting performance was observed. The initial limiting current level of the model FCL was 1.7 times higher than the critical current of the HTS element, and the fault current is suppressed to 52% immediately after the short‐circuit in the test. Considering voltage–current characteristics of a high‐T_C superconductor in a computer simulation, the calculated results almost agreed with the experimental results. © 1999 Scripta Technica, Electr Eng Jpn, 127(1): 31–38, 1999     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Electromagnetic analysis coupled with motion for high‐speed circuit breakers of eddy current repulsion using the tableau approach

Electromagnetic field analysis coupled with motion using the tableau approach has been applied to high‐speed circuit breakers of eddy current repulsion mechanisms. This breaker has an opening time of 1 ms and break time less than 1 cycle (20 ms). The driving part of the breaker is composed of electromagnetic repulsion mechanisms and disk springs with nonlinear characteristics. The mechanisms are composed of two fixed coils and one repulsion plate. A numeric experiment has been applied to investigate the dynamic behavior of the electromagnetic repulsion mechanism using the equivalent circuit method. Calculation results were in good agreement with both measurement results and calculation results by FEM on an experimental model. In addition, repulsive forces depending on material conductivities have been researched. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 152(4): 8–16, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20149     

Re‐ignition surge and high‐frequency arc extinction phenomena at 550‐kV shunt reactor current interruption

At substations connected with transmission lines and cables, shunt reactors are sometimes installed to compensate the capacitive current of these lines and cables. It is known that re‐ignitions occur and high‐frequency currents flow during interruption of the shunt reactor currents by switches. When the high‐frequency currents are interrupted immediately after the re‐ignitions (which is called high‐frequency arc extinction), the result is often repetitive re‐ignitions or voltage escalations that produce dangerous overvoltages. The authors investigated the occurrence of high‐frequency arc extinctions in a 550‐kV one‐break SF₆ gas circuit breaker during interruption of a 550‐kV shunt reactor current. Computations for a real 550‐kV substation gave a minimum frequency of 290 kHz for the high‐frequency current. However, 550‐kV reactor current interruption tests showed that high‐frequency arc extinctions did not occur even when this frequency was lowered to 26 kHz. Since high‐frequency arc extinction is generally likely to occur at lower frequencies, it was concluded that high‐frequency arc extinction will not occur in a 550‐kV one‐break SF₆ gas circuit breaker during interruption of shunt reactor current in real substations. © 2001 Scripta Technica, Electr Eng Jpn, 136(2): 18–25, 2001     

Development of a high‐speed laser interferometer using an acousto‐optic deflector

An acousto‐optic laser deflector was used as a shutter for high‐speed imaging of laser interference fringes using an ordinary CCD camera. The exposure duration was set by the pulse width of the high‐frequency signal applied to the acousto‐optic deflector. Changes in laser interference fringes due to an impulse discharge in air were obtained at an exposure duration of 4 µs. By applying a sequence of high‐frequency signals with different frequency, the beam was deflected to four different angles at different times, allowing four interference images to be captured on a single video frame. This was used for time‐resolved imaging of the interference fringe pattern. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 148(2): 76–83, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20011     

Design and analysis of low‐speed,high‐torque permanent magnet motors

This paper presents design and analysis of low‐speed, high‐torque permanent magnet motors. The motor has 16‐pole, 18‐coil construction, and a unique winding arrangement to produce high torque. The simplified torque analysis is proposed considering the line of magnetic induction distribution in the motor. The validity of the proposed analysis has been proved by both linear and nonlinear FEM analyses. The 500‐Nm, 200‐rpm test motor has been designed and constructed and the motor shows the expected characteristics. © 2000 Scripta Technica, Electr Eng Jpn, 132(3): 48–56, 2000     

Three‐dimensional finite element eddy current analysis by using high‐order vector elements

Sets of high‐order basis functions of a tetrahedral element are systematically constructed and applied to finite element analysis of eddy current problems. A polynomial space is divided into a lot of subspaces assigned on the edges, faces, and a volume of the tetrahedral element. Lagrange‐type vector basis functions of the subspaces are presented. The effect of the high‐order vector elements is investigated by a cubic conductor model located in AC steady‐state magnetic fields. In the calculations using the fundamental and second‐order elements, no convergent value of the eddy current power loss can be obtained in spite of fine meshes because the eddy current shifts to the surface of the conductor. The higher‐order vector elements give the convergent solutions in the coarse meshes. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 147(4): 60–67, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10306     

A new high‐frequency voltage injection method for sensorless drive of permanent‐magnet synchronous motors with pole saliency

This paper proposes a new sensorless vector control method for salient‐pole permanent‐magnet synchronous motors. In regard to rotor phase estimation, the sensorless vector control method is characterized by a new high‐frequency voltage injection method distinguished from the conventional ones by a unique ellipse shape of the spatial rotation, and by a new PLL method whose input is a high‐frequency current autocorrelated signal. The new vector control method established by two innovative technologies can have the following high‐performance and attractive features: (1) it can allow 250% rated torque at standstill; (2) it can operate from zero to the rated speed under the rated motoring or regenerating load; (3) it accepts instant injection of the rated load even for zero‐speed control; (4) it accommodates a load with huge moment of inertia; (5) phase estimation is very robust against inverter dead time; (6) the computational load for estimating rotor phase is very small, would be the smallest among the methods with comparable performance. This paper presents the new vector control method by focusing on two innovative technologies from its principles to design rules. Usefulness of the new vector control method is verified through extensive experiments. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 164(4): 62–77, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20632     

Signal separation using second‐ and high‐order statistics

This paper presents two methods for signal separation. In either method, the fundamental criterion for separation relies on reducing to zero, or at least minimizing, the output cross‐correlation or cross‐cumulant functions of a decoupling multi‐input–multi‐output system that is fed with mixed signals. In one of the approaches used, the parameters of this system are determined through solving — in a least‐squares sense — a linearized set of equations describing the deviations from zero of either the cross‐correlation or cross‐cumulant functions when evaluated for different lags. An alternative rapidly convergent adaptive algorithm is also described for minimizing the cross‐correlation or cross‐cumulant functions. The paper also considers both FIR and IIR representations of the decoupling system. It shows that using IIR functions in the decoupling system does not offer any merit over the FIR case. Illustrative examples are given to show the performance of the proposed algorithms. Copyright © 2000 John Wiley & Sons, Ltd.