An efficient piecewise‐linear DC analysis method for general non‐linear circuits

The convergence problems of conventional DC analysis can be partly avoided by using piecewise‐linear analysis. This paper proposes a piecewise‐linear DC analysis method that can efficiently handle arbitrary couplings between non‐linear circuit elements. Piecewise‐linear modelling of the non‐linear circuit elements is automatically performed during simulation, using simplicial subdivisions. The number of linear regions, and thereby iterations, is considerably reduced by combining the common parts of separate simplicial subdivisions. Due to these reasons and since the method is formulated with the commonly used modified nodal approach, it has been possible to implement the method in the general‐purpose circuit simulator APLAC. The correct operation of the method is demonstrated with three examples. Copyright © 1999 John Wiley & Sons, Ltd.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

On simplex‐based piecewise‐linear approximations of non‐linear mappings

Simplex‐based piecewise‐linear (PWL) approximations of non‐linear mappings are needed when the robust PWL analysis is used to directly solve non‐linear equations. This paper proposes a straightforward technique for transforming the well‐known approximations into another form. This new form is computationally more efficient, since it preserves the sparse structure of the original Jacobian matrix. Furthermore, this new form of PWL approximation explicitly relates the simplex‐based PWL analysis to the conventional formulation of the Katzenelson algorithm. The proposed transform technique is also extended to treat groupwise‐separable mappings and, finally, non‐separable but sparse mappings that arise in real‐life simulation of large electronic circuits. In this paper, all these (transformed) simplex‐based PWL approximations are compared in terms of their generality and efficiency. The computational efficiency of the PWL approximation that utilizes sparsity is validated with realistic simulations. Copyright © 2005 John Wiley & Sons, Ltd.     

Finding all solutions of piecewise‐linear resistive circuits using the dual simplex method

An efficient algorithm is proposed for finding all solutions of piecewise‐linear (PWL) resistive circuits using linear programming (LP). This algorithm is based on a simple test (termed the LP test) for non‐existence of a solution to a system of PWL equations in a given region. In the conventional LP test, the system of PWL equations is transformed into an LP problem, to which the simplex method is applied. However, this algorithm requires a very large number of pivotings because the simplex method is applied on many regions. In this paper, we introduce the dual simplex method to the LP test, which makes the average number of pivotings per region much smaller (less than one, for example) and makes the algorithm very efficient. By numerical examples, it is shown that the proposed algorithm could find all solutions of large‐scale problems, including those where the number of variables is 300 and the number of linear regions is 10³⁰⁰, in practical computation time. Copyright © 2002 John Wiley & Sons, Ltd.     

A novel compact piecewise‐linear representation

A new compact MAX representation for 2‐D continuous piecewise‐linear (PWL) functions is developed in this paper. The representation is promising since it can be easily generalized into higher dimensions. We also establish the explicit functional form of basis function and demonstrate that the proposed basis function is the elementary ‘building block’ from which a fully general 2‐D PWL function can be constructed. In addition, we reveal the relationship of basis function with minimal degenerate intersection and Hinging Hyperplane, which shows that the MAX model can unify Chua's canonical expression, Li's representation, lattice PWL function and Bremann's Hinging Finding Algorithm into one common theoretical framework. Copyright © 2005 John Wiley & Sons, Ltd.     

An efficient algorithm for finding all DC solutions of piecewise‐linear circuits

An efficient algorithm is proposed for finding all DC solutions of transistor circuits where characteristics of transistors are represented by piecewise‐linear (PWL) convex monotone functions. This algorithm is based on a simple test (termed the linear programming, LP, test) for non‐existence of a solution to a system of PWL equations in a given region. In the conventional LP test, the system of PWL equations is transformed into an LP problem by surrounding component PWL functions by rectangles. Then the dual simplex method is applied, by which the number of pivotings per region becomes very small. In this letter, we propose a new LP test using the dual simplex method and triangles. The proposed test is not only efficient but also more powerful than the conventional test using the simplex method or rectangles. Copyright © 2008 John Wiley & Sons, Ltd.     

Speed‐up and performance evaluation of piecewise‐linear DC analysis

The good convergence properties of piecewise‐linear (PWL) DC analysis have been thoroughly discussed in many papers. This paper, in turn, concentrates on the speed of PWL DC analysis, where the boundary crossing of linear regions plays a crucial role. Fast methods are presented for performing the following boundary‐crossing computations: LU‐decomposition update, matrix‐equation solution, boundary‐crossing direction, and damping‐factor determination. Special attention is given to those PWL DC analysis methods that perform PWL modelling of the non‐linear components on the fly; an adaptive method is proposed for controlling the accuracy of PWL modelling and speeding up simulation. The computational efficiency of the accelerated PWL DC analysis is discussed and compared with that of conventional, Newton–Raphson iteration‐based, DC analysis. Finally, the performance evaluation is completed with realistic simulation examples: it is demonstrated that the speed of the accelerated PWL DC analysis is comparable with that of the conventional DC analysis. Copyright © 2006 John Wiley & Sons, Ltd.     

Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.     

Current‐mode programmable piecewise‐linear neural synapses

Cellular Neural Networks with piecewise linear connection have been proposed by several authors as a generalization of the basic paradigm, which allows for more complex functionality. None of the prototypes realized to date, however, provides for such kind of synapses. As a feasibility study, a current‐mode subthreshold CMOS piecewise‐linear synapse circuit is developed in this paper. Copyright © 2003 John Wiley & Sons, Ltd.     

Performance evaluation of the LP test algorithm for finding all solutions of piecewise‐linear resistive circuits

In this letter, the performance of the LP test algorithm, which is an algorithm for finding all solutions of piecewise‐linear resistive circuits, is evaluated by numerical experiments. It is shown that the algorithm could find all solutions of large‐scale problems (including those where the number of variables is 200–300 and the number of linear regions is 10²⁰⁰–10³⁰⁰) in practical computation time. Copyright © 2000 John Wiley & Sons, Ltd.     

Improvement of the contraction‐type LP test algorithm for finding all solutions of piecewise‐linear resistive circuits

In this letter, an effective technique is proposed for improving the computational efficiency of the contraction‐type LP test algorithm, which is an algorithm for finding all solutions of piecewise‐linear resistive circuits. Using the proposed technique, all solutions of a large‐scale problem, where the number of variables is 100 and the number of linear regions is 10¹⁰⁰, could be found in less than 10 min using a 360 MHz computer. Copyright 2001 John Wiley & Sons, Ltd.     

An interval algorithm for finding all solutions of non‐linear resistive circuits

In this letter, an efficient algorithm is proposed for finding all solutions of non‐linear (not piecewise‐linear) resistive circuits. This algorithm is based on interval analysis, the dual simplex method, and the contraction methods. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500–700 non‐linear circuit equations in acceptable computation time. Copyright © 2004 John Wiley & Sons, Ltd.     

Bifurcation analysis of a piecewise smooth system with non‐linear characteristics

In previous works, there are no results about the bifurcation analysis for a piecewise smooth system with non‐linear characteristics. The main purpose of this study is to calculate the bifurcation sets for a piecewise smooth system with non‐linear characteristics. We first propose a new method to track the bifurcation sets in the system. This method derives the composite discrete mapping, Poincaré mapping. As a result, it is possible to obtain the local bifurcation values in the parameter plane. As an illustrated example, we then apply this general methodology to the Rayleigh‐type oscillator containing a state‐ period‐dependent switch. In the circuit, we can find many subharmonic bifurcation sets including global bifurcations. We also show the bifurcation sets for the border‐collision bifurcations. Some theoretical results are verified by laboratory experiments. Copyright © 2005 John Wiley & Sons, Ltd.     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

A method for the approximate synthesis of cellular non‐linear networks—Part 2: Circuit reduction

In this paper, we face the problem of model reduction in piecewise‐linear (PWL) approximations of non‐linear functions. The reduction procedure presented here is based on the PWL approximation method proposed in a companion paper and resorts to a strategy that exploits the orthonormality of basis functions in terms of a proper inner product. Such a procedure can be favourably applied to the synthesis of the resistive parts of cellular non‐linear networks (CNNs) to reduce the complexity of the resulting circuits. As an example, the method is applied to a case study concerning a CNN for image processing. Copyright © 2003 John Wiley & Sons, Ltd.     

A combined approach for the identification of continuous non‐linear systems

The identification of a non‐linear continuous output‐only system from a time series is considered for the case that the functional form of the model is not known beforehand. To estimate both functions and parameters, a combination of non‐parametric modelling based on non‐linear regression and parametric modelling based on a multiple shooting algorithm is proposed. This strategy to determine non‐linear differential equations is exemplified on experimental data from a chaotic circuit where an accurate reconstruction of the observed attractor is obtained. Copyright © 2003 John Wiley & Sons, Ltd.     

Non‐linear analog circuit fault diagnosis with large change sensitivity

Large change sensitivity has been proved efficient at, but restricted to, generating a linear circuit fault dictionary. This paper discusses the extension of large change sensitivity to non‐linear analog circuit fault diagnosis. The fault dictionary is divided into d.c. and a.c. sections. In the d.c. domain, non‐linear components are approximated with piecewise linear models. By relating the operating region of each piecewise linear model to the magnitude of a single fault in a procedure termed preconditioning, it is shown that large change sensitivity can efficiently compute the response of a faulty non‐linear circuit. Results presented of an analysis of computational complexity show a significant reduction in the cost of simulating single linear resistor faults in a non‐linear circuit using this method. In addition, after establishing that the resistive portion of the circuit is fault free, a fault dictionary is constructed for dynamic components using large change sensitivity in the small signal a.c. domain. Included with a discussion on the issues of large change sensitivity based simulation‐before‐test, a small non‐linear circuit is used to demonstrate the effectiveness of the proposed fault diagnosis algorithm. Copyright © 2000 John Wiley & Sons, Ltd.     

Comparison of HEMT non‐linear model extraction approaches based on small signal and on large signal measurements

In this paper the extraction of a non‐linear model for a HEMT is undertaken by means of two different approaches. The first approach is the classical procedure that consists of using the small signal data to fully generate a non‐linear model. The second alternative is developed following a different tactics that uses directly the response of the device to a large signal stimulus. Both approaches are compared in terms of required extraction measurements and limits of application. Copyright © 2002 John Wiley & Sons, Ltd.     

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi‐input multi‐output (MIMO) piecewise‐affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90‐nm complementary metal‐oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high‐performance and minimum unitary cost are required. Copyright © 2015 John Wiley & Sons, Ltd.