Injection transistor logic (ITL): new bipolar low-power inverter

Investigates the characteristics of a new injection transistor logic (ITL) fabricated by vapour-phase epitaxy and ion implantation. The maximum current gain of the Si-ITL-inverter is about 150. The propagation delay t/sub pd/ was determined by the ring oscillator and maximum frequency method. At a power of 100 mu W per gate for this inverter, t/sub pd/ is about 500 ps and 850 ps for 60 mu W. In the high-speed ITL structure t/sub pd/ is about 300 ps for 120 mu W.<>     

Analysis of heterojunction bipolar transistor/resonant tunnelingdiode logic for low-power and high-speed digital applications

A high-speed digital logic family based on heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) is proposed. The negative differential resistance of RTDs is used to significantly decrease the static power dissipation. SPICE simulations indicate that propagation delay time below 150 ps at 0.09-mW static power per gate should be obtainable     

Simultaneous power supply, threshold voltage, and transistor sizeoptimization for low-power operation of CMOS circuits

This paper demonstrates a new approach for minimizing the total of the static and the dynamic power dissipation components in a complementary metal-oxide-semiconductor (CMOS) logic network required to operate at a specified clock frequency. The algorithms presented can be used to design ultralow-power CMOS logic circuits by joint optimization of supply voltage, threshold voltage and device widths. The static, dynamic and short-circuit energy components are considered and an efficient heuristic is developed that delivers over an order of magnitude savings in power over conventional optimization methods     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

Lifetime prediction for submicrometer LSI circuits and programmable logic: An overview

An overview is given of the experience gained in lifetime prediction for submicrometer LSI circuits and programmable logic, as reported by leading manufacturers including Siemens AG, Analog Devices, Atmel, Xilinx, Altera, QuickLogic, and Actel. The main conclusions are as follows: (i) The Arrhenius equation remains a major tool for describing the temperature dependence of circuit lifetime. (ii) The lifetime of LSI circuits continues to display a bimodal pattern. (iii) Bias-temperature stressing constitutes a generally useful technique for identifying failure mechanisms. (iv) The chi-squared distribution should be employed in predicting useful-life failure rate.Translated from Mikroelektronika, Vol. 34, No. 2, 2005, pp. 138–158.Original Russian Text Copyright © 2005 by Strogonov.     

Noncomplementary BiCMOS logic and CMOS logic for low-voltage,low-power operation-a comparative study

This paper presents results of a comprehensive comparative study of six bipolar complementary metal-oxide-semiconductor (BiCMOS) noncomplementary logic design styles and two CMOS logic styles for low-voltage, low-power operation. These logic styles have been compared for switching power consumption and power efficiency (power-delay product). The examination offers two alternative approaches never used in other comparative studies. First, all BiCMOS-based styles are compared to low-power CMOS styles as opposed to a single conventional static CMOS style. Second, a low-power methodology has been used as opposed to performance methodology referred to in the previous logic comparisons. The styles examined are bootstrapped BiCMOS, bootstrapped full-swing BiCMOS, bootstrapped bipolar CMOS, Seng-Rofail's bootstrapped BiCMOS, modified full-swing BiCMOS, dynamic full-swing BiCMOS, double pass-transistor CMOS, and inverter-based CMOS. These design styles have been compared at various power supply voltages (0.9-3 V), with various output load capacitances (0.1-1 pF) at the frequency 50 MHz and temperature 27°C. The results clearly show which logic style is the most beneficial for which specific conditions     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Diode and transistor equivalent circuits for transient operation

Solid-state devices have complex energy storage effects that complicate their transient operation. A frequently used method of analysis is that of charge control. This method relies upon quasi-static equilibrium and may have significant errors for high-speed operation. The method proposed uses a series approximation to a convolution integral solution. The first term of the series is equivalent to charge-control operation and higher order terms provide improved accuracy in terms of lumped elements of an equivalent circuit, but the real merit of the series form is its ready adaptability to computer- programmed node-branch circuits analysis.     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.     

Optimising nanometric CMOS logic cells for low-power,low-energy,and noise margin

In this paper, we present a multi-objective optimisation technique for transistor sizing in the variation-prone nanometric complementary metal-oxide semiconductor (CMOS) logic cells. To demonstrate the effectiveness of the technique, we have used the common figures-of-merit, such as power, energy, and static noise margin. By using examples of different logic cells, we have demonstrated how competing design goals can be tackled effectively. We show that concurrent improvements in multiple figures-of-merit are possible using the proposed method.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

CO2激光测距机用智能化计数逻辑及控制电路

本文介绍了一种CO2激光测距机用智能化计数逻辑及控制电路,该电路也可用于一般脉冲式激光测距机。     

Energy per logic operation in integrated circuits: definition and determination

A figure of merit for the comparison of different types of logic circuits on the basis of inverters is presented. This figure of merit-the minimum energy per logic operation-is equal to the product of the time period necessary for carrying out a logic operation times the power which is fed into the inverter during this time period. Methods for the determination of these terms by ring oscillator measurements and model calculations are considered. In contrast to the so-called `delay-power' product, these newly defined terms are independent of the kind of measurement, as for example the number of stages of the ring oscillator. Thus the minimum energy per logic operation is an intrinsic figure of merit which allows a qualitative comparison of different types of logic circuits on a physical basis.     

Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic

Dynamic logic is susceptible to noise, especially in the ultra-deep submicrometer dual threshold voltage technology. When the dual threshold voltage is applied to the domino logic, noise immunity must be carefully considered since the significant subthreshold current of the low threshold voltage transistor makes the dynamic node much more susceptible to noise. In the first part of this paper, we introduce a new keeper transistor sizing method to determine the optimal keeper transistor size in terms of speed, power, and noise immunity. With the use of data obtained by presimulation, it is unnecessary to simulate all the design corners corresponding to the feasible NMOS evaluation transistor size ranges to find the optimal keeper transistor size. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all the domino logic gates. In the second part of this paper, we propose a new dual threshold voltage domino logic synthesis with the keeper transistor sizing to minimize the power consumption while meeting delay and noise constraints. With the optimal keeper transistor size determined by the proposed keeper transistor sizing method, the dual threshold voltage assignment to domino logic can be simplified to the discrete threshold voltage selection. Experimental results for ISCAS85 benchmark circuits show significant savings on leakage power and active power.     

面向时间同步网络开通运维的智能时钟解决方案

本文提出了基于SDN的端到端的智能时钟网络架构和解决方案,该方案可以自动准确地进行同步规划,快速高效地发现现网配置隐患,进行自动同步恢复和告警定位,并实现同步性能实时监控,从而全面支撑时间同步网络的开通运维.     

Resonant tunneling transistor lasers: A new approach to obtain multi-state switching and bistable operation

Bipolar resonant tunneling heterotransistor structures, which can be configured to operate as multi-state or as bistable lasers, are described. Both edge and surface-emitting structures are presented. Computations of various optoelectronics parameters including confinement factor, threshold current density, and cavity modes for a stripe-geometry structure are presented. In addition, simulations of base and collector currents are given for a resonant tunneling transistor to demonstrate the feasibility of lasing in the base region.     

Trends in network and service operation for the emerging future Internet

Recent advances in disruptive technologies, such as P2P content distribution, and research in high-speed optical and wireless transmission and in the virtualization of systems have sparked fundamental discussions about how to design the future Internet: Is a clean-slate approach mandatory? Would an evolutionary process be more appropriate? What kind of network and application features will drive the design of the future Internet? The aims of this position paper are to outline the technological trends and challenges for the emerging future Internet and to discuss the requirements and implications.     

智能运维平台协同过滤信息推荐系统设计

针对以往使用的内容过滤推荐系统、数据挖掘技术推荐系统难以区分信息属性,导致系统不同分区所占比例与实际不符,出现推荐精准度低的问题,提出了智能运维平台协同过滤信息推荐系统设计.根据系统硬件结构,从超文本服务器中阅读位置信息,构建索引器,在同一上下文中,正向索引和反向索引关键词.使用华为云Stack8.0平台中央处理器,设...