构建高可用的安全网络--DawningGate多重链接技术

前 言对国有大型企业的CEO、CFO、CIO们来说,信息安全已日益成为他们最为关注的问题之一。我国已加入WTO,而且Internet的触角已快速延伸到社会的每一个角落,所以,对每一个“在线”商务来说,安全问题都是不可避免的。许多因素影响着企业对信息安全的需求:在线用户的爆炸性增长,分布式系统处理能力的增强,以及网络带宽的快速拓展,这些构成了企业电子商务运作的环境。在这种大气候下,电子商务的发展迅猛,然而机遇与风险并存,对企业的威胁和风险也是在同步增长的。企业的管理者们开始考虑如何在企业发展的同时保护其安全的成长。由于安全…     

A highly reliable mask inspection system

An automatic system for inspecting micro mask defects with 1-µm minimum detectable size has been developed. An outline of the system is as follows: The pattern image obtained with a pickup tube is converted into binary video signals which are transferred into two parallel logic circuits for detecting pattern defects. One is based on the pattern-analyzing method, for which one of four algorithms for detecting micro defects is presented in detail. The other is based on the design-pattern data-comparing method, where the data compression scheme and a new idea for avoiding mask alignment errors are adopted. A software system outline, very important in assisting the hardware functions in this system, is also presented. The results of experiments for determining system performance indicate that the system can detect ≥1-µm diameter defects or loss patterns with high probability by complimentary use of the two methods. A 4-in by 4-in mask can be inspected within 100 rain.     

A highly reliable and long life cathode

 A highly reliable and long life cathode is described.The emission current density of the cathode is higher than 400mA/cm~2 at 730℃,and has a value of 50—70mA/cm~2 at 550℃.The life of the cathode under different conditions is over 70000hrs,The result of oxygen poisoning test is also given.     

塑封IC常见失效及对策

本文探讨了塑封IC常见失效分析步骤、失效分析手段以及提高可靠性采取的措施：     

Word-line architecture for highly reliable 64-Mb DRAM

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement and a 0.3~1.8-V larger word-line voltage margin to write ONE data into the cell     

Development of highly reliable Al-Si-Pd alloy interconnections forVLSI

An Al-Si-Pd alloy developed to improve the reliability of VLSI interconnections is discussed. Dry etching characteristics of the Al-Si-Pd alloy in submicrometer patterning proved to be much better than those of the Al-Si-Cu alloy used previously. Both electro- and stress-induced migration resistances of the Al-Si-Pd alloy were at least at the same level as those of the Al-Si-Cu alloy. Long-term reliability tests of resin-molded 1.3-μm-process MOS devices using an Al-Si-Pd alloy interconnection gave satisfactory results     

A novel self-aligned highly reliable sidewall split-gate flash memory

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.     

Drain structure optimization for highly reliable deep submicrometern-channel MOSFET

A guideline for n^- fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n^- design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n ^- extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n^- extension region. Furthermore, it was also confirmed that the 0.3 μm optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance     

Novel concept for highly reliable DC/DC convertors

A new type of zero switching DC/DC convertor has been developed to meet rigorous requirements for transoceanic optical cables. Its circuit is noteworthy for the small number of components used, and for the pseudoresonant mode of operation at frequencies above 300 kHz     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

武器装备通信系统高可靠设计

基于RS-485芯片设计了武器系统的通信网络,实现了武器系统的高可靠通信.从硬件与软件两个方面详细阐述了本系统的可靠性设计.实际应用表明该系统可靠性、兼容性好,而且结构简单、造价低廉、控制方便.     

FTMP—A highly reliable fault-tolerant multiprocess for aircraft

FTMP is a digital computer architecture which has evolved over a ten-year period in connection with several life-critical aerospace applications. Most recently it has been proposed as a fault-tolerant central computer for civil transport aircraft applications. A working emulation has been operating for some time, and the first engineering prototype is scheduled to be completed in late 1979. FTMP is designed to have a failure rate due to random causes of the order of 10^-10failures per hour, on ten-hour flights where no air-borne maintenance is available. The prefered maintenance interval is of the order of hundreds of flight hours, and the probability that maintenance will be required earlier than the preferred interval is desired to be at most a few percent. The design is based on independent processor-cache memory modules and common memory modules which communicate via redundant serial buses. All information processing and transmission is conducted in triplicate so that local voters in each module can correct errors. Modules can be retired and/or reassigned in any configuration. Reconfiguration is carried out routinely from second to second to search for latent faults in the voting and reconfiguration elements. Job assignments are all made on a floating basis, so that any processor triad is eligible to execute any job step. The core software in the FFMP will handle all fault detection, diagnosis, and recovery in such a way that applications programs do not need to be involved. Failure-rate models and numerical results are described for both permanent and intermittent faults. A dispatch probability model is also presented. Experience with an experimental emulation is described.     

A highly reliable GaInAs-GaInP 0.98-μm window laser

A novel window structure realized by selective N ion implantation and subsequent rapid thermal annealing has been applied to overcome the catastrophic optical damage (COD) of a GaInAs-GaInP laser emitting in the 0.98-μm wavelength region. A kink-free output power up to 220 mW at 25°C was obtained. Laser characteristics including the I-L, far-field pattern, and lasing spectrum were almost the same as those of a conventional nonwindow laser consisting of the same structure except for the window region. In a 50°C, APC-150 mW aging test, the window lasers have operated stably beyond 16 000 h, and no damage has been observed. Under this aging condition, a median lifetime of 280 000 h was obtained from log-normal plotting of aging characteristics. This marked improvement in reliability is due to a remarkable increase of damage tolerance realized by the window structure. In addition, there was minimal change in the characteristic of the window laser during the aging, indicating the absence of serious inner degradation. These results clearly show that our 0.98-μm window laser suppresses both COD failure and inner degradation satisfactorily and can be used in practical applications     

一个高可靠性的短路保护电路设计及其应用

针对负载短路或过载都会对线性稳压器造成性能不稳定或损坏.在限流型保护电路的基础上,采用TSMC0.18μm,设计并验证了一个高可靠性的短路保护电路.该短路保护电路采用电流镜电路按一定比例复制整流管电流,再通过采样电阻转变成相应的电压,最后通过反馈电路实现短路保护功能.ADS仿真结果表明,即使地平面存在大量噪声,只要发生负载短路,就能有效地关断线性稳压器,并可靠地维持其关断的状态.当负栽短路消除后,系统将自动恢复到正常工作状态.     

A highly reliable trench DMOSFET employing self-align technique andhydrogen annealing

A novel process technique for fabricating trench double diffused MOSFETs (DMOSFET) using three mask layers is realized in order to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. A unit cell with a cell pitch of 2.3~2.4 μm and a channel density of 100 Mcell/in² are obtained. Specific on-resistance is 0.36 mΩ.cm² is obtained with a blocking voltage of 43 V. The highly reliable trench DMOSFET was obtained by the formation of the corner rounding of the hydrogen annealed trench surface     

A highly stable and reliable wavelength monitor integrated laser module design

Three existing wavelength monitor integrated laser module designs are evaluated. The shortcomings of these designs are resolved by a unique design that eases alignment tasks and greatly enhances the wavelength stability and the wavelength tunability. For example, the wavelength drift over case temperature is 16 times smaller than the best result of previous reports. With the incorporation of thermal compensation, the temperature-induced wavelength drift of the etalon is eliminated. In anticipation, this design enables a worst overall wavelength-drift of 4.41 pm after 25 years of usage to be achieved.     

高可靠熔断器步进电应力极限评估试验

介绍了高可靠熔断器极限评估技术的提出背景,分析其熔断机理,设计了熔断器电流步进极限评估试验,考察熔断器在电应力下的热平衡状态和可靠性水平;并选用国产典型型号的宇航用高可靠熔断器,对设计的试验方法进行了验证,结果显示本试验方法合理可行,从而为规范熔断器极限评估试验方法提供了基础和依据。     

Electrical properties of highly reliable 32 Mb FRAM with advanced capacitor technology

Highly reliable 32 Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The highly (1 1 1) oriented ferroelectric films were fabricated by the optimized annealing method, which generates large remnant polarization. In addition to the double annealing process for sol–gel derived ferroelectric films, advanced capacitor technology of CVD process was developed for achieving strong retention properties. The CVD technique provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and large sensing margin. After baking test at 150 °C for 100 h, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.     

Analysis and design of a highly reliable transport architecture forISDN frame-relay networks

The authors explore control strategies in the design of a high-performance transport architecture for integrated services digital network (ISDN) frame-relay networks. For real-time congestion control, buffer management, priority queueing, adaptive windowing, and selective frame, discard policies are described that can effectively maximize network efficiency while preventing unfair usage of shared network resources. Virtual-circuit routing strategies are proposed that ensure an efficient distribution of traffic loads across the network despite variations in traffic patterns and topology changes. It is shown that source routing provides significant performance benefits over link-by-link routing, particularly in large networks that are not so densely connected. Routing table update and call acceptance mechanisms are described that provide for efficient bandwidth management in the network. Fault-tolerant strategies are described that include fast failure detection and local reroute. These strategies are capable of restoring affected virtual circuits in less than 10 s, which is adequate for session maintenance under most application scenarios