Plastic packages survive where hermetic packages fail

Plastic encapsulation is now a highly reliable method of packaging microelectronics and can be significantly more reliable than military specified “hermetic components” in field deployments of electronics in humid tropical climates. MIL883 hermeticity is an inadequate safeguard against penetration by high levels of moisture in the atmosphere. In this new work, tropical climates are analysed and shown to be significantly more severe than those safeguarded by current MIL883 standards. Field failure returns have revealed that MIL 883 hermetic CerDIP (ceramic dual-in-line) packaged ICs installed in digital switching systems failed catastrophically with a failure rate of 1755 FITs. The cause of failure was severe ingress of moisture, resulting in dewpoints up to 30°C. Alternative indigenous developments of modular digital switches for widespread rural use in India have incorporated plastic encapsulated components selected according to the criteria developed from earlier extensive and successful reliability work by British Telecommunications (BT). Such criteria include the use of HAST (highly accelerated stress technique, invented at BT Labs). The BT Labs pioneering work demonstrated that commercial transfer-moulded epoxy packaged devices from certain sources were more reliable than their hermetic counterparts.Evidence from other published pioneering work has confirmed that plastic packaging now endures as a high reliability method of packaging microelectronics. Such pioneering work is also reviewed in this paper. In the USA, the IEEE Gel Task Force followed the earlier BT Laboratories initiative and concluded that silicone gels are indeed suitable for high reliability applications. AT&T undertook comprehensive materials analyses to show that silicone gels possess remarkably useful properties to safeguard high reliability integrated circuits. CALCE, University of Maryland, conducted studies of simple logic circuits and showed that the achieved reliability in temperature climatic conditions is three times greater than that predicted for military parts. BT Labs continued its work and extended its applicability to optoelectronics. Analyses of MCM applications for satellites by the author also show that plastics are a preferred option. The evidence is that plastic encapsulation is now a very reliable and cost-effective option.     

MEMS中的封装技术研究

MEMS中的封装工艺与半导体工艺中的封装具有一定的相似性 ,因此 ,早期MEMS的封装大多借用半导体中现成的工艺。本文首先介绍了封装的主要形式 ,然后着重阐述了晶圆级封装与芯片级封装[1] 。最后给出了一些商业化的实例     

提高多芯片微波模块气密性的研究

伴随着现代微电子技术的高速发展,在一些特殊环境条件下使用的各种微波模块,需要进行密封封装,以防止器件中的电路因潮气、大气中的离子、腐蚀气氛的浸蚀等引起失效,采用气密性封装以延长器件的使用时间。密封的实现方式根据具体要求采取不同的措施,对于密封要求相对较低,可以采用锡封的方式实现;对于密封要求相对较高的,可以采用平行封焊的方式实现。影响平行缝焊质量的有诸多因素,盖板与平行缝焊的关系是相当重要的,在壳体性能稳定的情况下,盖板质量的好坏直接影响着器件的气密性,盖板和管壳之间的匹配、工艺参数的设置、电极表面的状态等对平行缝焊的质量都起着重要的作用。     

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

Some emerging microelectromechanical systems (MEMS) devices such as high-performance inertial sensors and high-speed actuators must be operated in a high vacuum and in order to create this vacuum environment, specific packaging is required. To satisfy this demand, this paper presents a novel method for hermetic and near-vacuum packaging of MEMS devices. We use wafer-level bonding technology to combine with vacuum packaging, simultaneously. For this packaging solution, the wafers with air-guided micro-through-holes were placed on a custom-built design housed in a vacuum chamber maintained at a low-pressure environment of sub-10 mtorr. Packaging structure is then sealed by solder ball reflow process with the lower heating temperature of 300degC to fill up micro-through-hole. Experimental results shown the hermetical packaging technique using solder sealing is adapted to the wafer-level microfabrication process for MEMS devices and can achieve better yield and performance. Thus, this technique is very useful for many applications with high performance and low packaging cost can be obtained due to wafer-level processing.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物。COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连。研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响最小。对用于标准的COF工艺的融除程序进行分析和特征描述,以便设计一种新的对裸露的MEMS器件热损坏的潜在性最小的程序。COF/MEMS封装技术非常适合于诸如微光学及无线射频器件等很多微系统封装的应用。     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物.COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连.研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响...     

An embedded overlay concept for microsystems packaging

An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.     

Quasi hermetic packaging for new generation of spaceborn microwave equipment

This paper presents the introduction of the quasi hermetic encapsulation of microwave hybrids for space application through different approaches evaluated at Thales Alenia Space – France. Thanks to the improvement for many years of microwave organic materials, it is now realistic to propose advanced packaging solutions like the chip on board approach with glob top encapsulation of active devices directly bonded on printed circuit boards for space applications. To validate this packaging approach, very significant reliability test-plans have been proposed and performed on the different technological processes and materials in agreement with standard space quality requirements. Results will be presented and a discussion on the nature of the stresses applied during the tests will be proposed.     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Conformal Hermetic Sealing of Wireless Microelectronic Implantable Chiplets by Multilayered Atomic Layer Deposition (ALD)

A hermetic sealing method of sub‐millimeter‐sized microelectronic chiplets for wireless body implants is presented by ultrathin and electromagnetically transparent atomic layer deposition (ALD) coatings. Fully 3D conformal encapsulation of wirelessly powered microdevices is demonstrated both with and without opening windows for electrophysiological measurements. The chiplets embedding custom application‐specific integrated circuits (ASICs) with radio frequency (RF) transmitters are encapsulated by a stack of alternating layers of hafnium oxide and silicon dioxide to maximize impermeability of water and ionic penetration while minimizing the volume of the packaging material. The hermeticity of the devices is characterized through accelerated aging tests in saline at T = 87 °C, while continued functionality is monitored via evaluation of backscattered RF signals (near 1 GHz) to ascertain possible degradation and electronic failure. Earliest failures of wirelessly functional devices occur after more than 180 d of immersion at 87 °C. Wireless devices having opening windows through the ALD envelope show no signs of degradation for >100 d. This implies an equivalent lifetime >10 years at T = 37 °C. This approach is readily scalable to high throughput batch processing of hundreds of microchiplets, offering a methodology for hermetic packaging of microscale biomedical chronic implants.     

用低温圆片键合实现传感器和微电子机械系统器件的集成和封装

集成化是传感器和微电子机械系统(MEMS)的发展方向,即将传感功能、逻辑电路和驱动功能集成在一块单芯片上。未来的系统芯片将能通过集成的传感器和逻辑电路收集并分析外界数据,将这些数据传输到中央处理器并产生必要的动作或反应。讨论了这种系统集成芯片对于封装和集成的要求,并提出一种能够满足这种要求的低温键合技术。同时这种低温键合技术还具有气密性封装、保留透明窗口等优点。     

Characterisation of chip-on-board and flip chip packaging technologies by acoustic microscopy

In recent years scanning acoustic microscopy (SAM) has been found to be a very successful technique when used in the microelectronics industry to evaluate, from a reliability perspective, standard plastic packaging technologies such as PQFP's, PLCC's, DIP's and SOP's. Very little research has been reported in the application of SAM as a technique for determining the quality and reliability of packaging technologies such as Chipon-Board (COB) and Flip Chip adhered devices, however. These areas will be addressed in this paper.     

A Study of Accelerated Storage Test Conditions Applicable to Semiconductor Devices and Microcircuits

This preliminary theoretical study on the application of accelerated stress testing for determining storage life of semiconductor devices and microcircuits has resulted in the following conclusions: There are more environmental stresses that can be applied to the accelerated testing of plastic encapsulated microcircuits, than hermetic devices. For hermetic devices, the assurance of initial hermeticity and wire bond integrity should insure long storage-dormancy life. Since only limited storage-dormancy data are available, accelerated testing and verification with use conditions data are necessary to support the conclusion of this study.     

Reliability of new packaging concepts

Today, most of the microelectronics packaging needs are met by semiconductor devices in plastic surface mount (SM) packages. Microelectronics packaging of the future will be either bare chip or chip size/scale packaging (CSP). Of the 45 billion SM packaged ICs to be manufactured in 2000, CSPs will be a small 3.4% but growing at 62% (compound annual growth rate). The use of direct bonded chip-on-board and flip chip (FC) technology for custom solutions may not match the growth of CSPs. The popcorn problem of existing plastic packages has been solved in many ways including the use of hydrophobic composite encapsulants as the best solution and thorough bake-out and storage as the long-standing practical solution. The popcorn problem which was more severe with the smaller and thinner encapsulations of CSPs is also solved with modern hydrophobic materials and new non-paddle package designs. Further, there is good evidence that reliability is not impaired even by delaminations in the bulk of the encapsulations – small delaminations being an inevitable consequence of stress relaxation following transfer moulding. CSP and FC bump joint reliability is safeguarded both by good soldering practice and by effective underfill. High reliabilities are achievable with the range of new packages built from modern materials, with random failure rates down to 10 failure units, infant mortalities controlled to low levels by six sigma manufacturing processes and wearout lifetimes exceeding 100 years even in tropical operation.     

表面镀层对封帽质量的影响

气密封装工艺技术是混合电路制造的关键技术。在可靠性要求较高的场合,对混合电路产品提出了水汽含量、漏气率和粒子碰撞噪声检测(PIND)合格率的指标要求。封装内部的多余物对电子器件的可靠性带来严重影响。主要从盒体的表面镀层方面进行讨论,分析了不同的金属化结构和不同的镀层厚度对气密封装的影响。实验表明,当封装使用的压力较大时,化学镀镍外壳的镀层容易出现裂纹,造成外壳锈蚀。外壳使用化学镀镍、电镀金结构时,其PIND不合格率较高。当镀层厚度超标时,不仅PIND不合格率较高,也会出现漏气问题。     

集成电路封装用绝缘胶漏电失效分析

在电子元器件封装领域中,塑封器件正逐步替代气密性封装器件。目前工业级塑封器件已不能满足器件的高可靠性要求,工业级塑封器件在严酷的环境应力试验中经常出现失效。研究了工业级塑封器件在可靠性筛选试验中出现失效的问题,通过X射线观察和芯片切面分析等方法,查明了造成器件失效的原因,并提出了优化改进措施。     

MEMS局部加热封装技术与应用

随着半导体技术的发展,封装集成度不断提高,迫切需要发展一种低温封装与键合技术,满足热敏器件封装和热膨胀系数差较大的同质或异质材料间的键合需求。针对现有整体加热封装技术的不足,首先介绍了局部加热封装技术的原理与方法,然后对电流加热、激光加热、微波加热、感应加热和反应加热等几种局部加热封装技术进行了比较分析,最后具体介绍了局部加热封装技术在热敏器件封装、MEMS封装和异质材料集成等方面的应用。由于局部加热封装技术具有效率高、对器件热影响小等优点,有望在MEMS技术、系统封装(SiP)、三维封装及光电集成等领域得到广泛应用。     

Thin film dielectric materials for microelectronics

Important applications of dielectric films used in modern integrated circuit technology include dielectric insulation, surface passivation, diffusion masking, radiation resistance, and hermetic seal. These many functional applications pose stringent requirements on the various properties of the insulating films and the methods used for their preparation. To date silicon dioxide (SiO2) has been used almost exclusively because of 1) its ease of preparation, 2) its well-understood properties, and 3) its generally good compatibility and satisfactory interface with silicon. There are, however, drawbacks to the use of SiO2and other materials have been sought for better performance, greater versatility, higher reliability, and lower cost. These include binary metal oxides and silicon nitride. The state of the art of thin film dielectric materials for microelectronics is reviewed in this paper. The role of thin film dielectrics for devices is presented, and new and known materials are discussed for potential applications.     

防静电工作表面：发展和历史（四）

直到20世纪50年代，电子设备和元件还是相当粗糙的系统，很少用到静电防护。它们能吸收很大的电荷而没有太大的电压提升，这种情况随着20世纪60年代初集成电路的发展而发生了根本的改变。紧随这些早期的集成电路之后的是各种薄膜器件和更密集更小的集成电路。薄膜电路和集成电路对静电放电敏感，原因是由于它们物理和电质量小和其不能承受低至100V过压的缺陷，据报道，一些较新的芯片能被低于10V的电压毁坏。也同时出现了另一个根本的改变——合成塑料的广泛使用，可以维持1000V或更高的静电电荷集结。确实，这样的值目前在塑料包装和工作表面上经常观测到，对付静电和抑制其对电子元件损坏能力需要电子设备制造商和用户长期保持警惕。     

Qualification of plastic encapsulated microcircuits (PEM) for avionicsBased on ``Plastic Encapsulated Microcircuits (PEM) Qualification Testing'''', by J. A. Scalise, which appeared in the Proceedings of the 46th Electronic Components and Technology Conference, Orlando, FL, U.S.A., 28–31 May 1996, pp. 392–397. © 1996 IEEE.

Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly accelerated stress test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP) and plastic dual-in-line (PDIP).Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by type of compound, passivation (including die coat) and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.