A failure analysis methodology for revealing esd damage to integrated circuits

A range of chemical and physical techniques is required in order to identify the failure sites and failure machanisms of ICs subjected to ESD transients. The damage features of ESD failures from the field are shown to be similar to those produced by simulated human-body-model testing. A curve tracer technique can be used to predict the location of an ESD failure site in the input or output circuit of an IC. Junction shorts induced by ESD transients form as a result of a combination of heating at the site of second breakdown, together with the heat generated by the discharge current in the discharge path. The ESD sensitivity of a given input or output circuit is dependent on the spacing between the input contact window. and the contact window of the nearest diffusion-to-Vss metallization.     

多层次模拟电路随机变异生成方法研究

针对目前复杂电路测试、诊断过程中故障样本获取困难的问题,提出一种随机变异生成策略。首先定义适用于随机方法的8种限定变异算子,可覆盖实际电路中的大多数真实故障;然后应用层次分析法(AHP),分别考虑电路组成元素间的相对故障概率和故障类型,计算出不同变异位置以及对应变异算子的被选权重;考虑连续型故障参数的分布,通过随机采样确定具体的参数值,使故障模型更为真实;最后,以一个串联调整型稳压电路为实例,为其生成500个随机变异体。实验结果表明:该方法能够快速有效地为多层次模拟电路生成大规模、高质量的故障样本。     

A framework for design and testing of analog integrated circuits

A global methodology for analog and mixed analog-to-digital VLSI design requires close interaction between simulations, CAD tools, measurements, and testing. An integrated hardware and software environment (framework) that implements this methodology in a systematic way is described. As an example of its application, the modeling of errors in multistage analog-to-digital converters (ADCs) is described. The framework has a unique software organization designed to facilitate the interpretation of measurement results and the feedback of information to the design world. The perfectly modular nature of the software makes it easy to gain a fundamental understanding of error mechanisms. In the ADC example, this understanding eliminates the need to probe internal parts of a circuit since information on internal errors can be recovered from external measurements     

Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

As the electronics industry continues to grow, technology feature sizes continue to decrease, and complex systems and levels of integration continue to increase, the need for better and more effective methods of testing to ensure reliable operations of chips, the mainstay of today's all digital systems, is being increasingly felt. One obvious way to significantly improve the testability of digital VLSI circuits and save testing time is to use built-in self-testing (BIST), where the basic idea is to have the chip test itself. BIST is a design methodology that combines the concepts of built-in test (BIT) and self-test (ST) in one, termed BIST. This technique generates test patterns and evaluates test responses inside the chip system, and has been widely used in many commercial VLSI products with appreciable success. The subject paper endeavors to present a comprehensive overview of the general methodology of BIST from its various perspectives, and in the sequel attempts to relate its significance in the particular context of modern embedded cores-based system-on-chip (SOC) technology.     

Development of a multitechnology field-programmable gate array suitable for photonic information processing

The architecture of a novel, multitechnology field-programmable gate array (FPGA) is introduced. Based on conventional complementary metal-oxide semiconductor VLSI technology this architecture has demonstrated the feasibility of reconfigurable and programmable hardware for prototyping photonic information processing systems. We report that this new FPGA architecture will enable the design of reconfigurable systems that incorporated technologies outside the traditional electronic domain. The smart photoreceivers monolithically integrated in the new FPGA architecture can receive optically encoded signals in parallel and process them with user programmable logic hardware.     

分形特征的模拟电路故障诊断方法

针对模拟电路中存在的非线性问题,提出一种以模拟电路分形特征为输入量的故障诊断方法。通过对多测试分量数据进行分形特征提取,输入神经网络建立信息融合中心融合处理各分形特征量,利用多源性互补信息减少模拟电路故障诊断的不确定性。实验结果表明,该故障诊断方法可准确地检测出模拟电路中的故障现象。     

两种实现数字化相控的电路

本文介绍了两种实现数字化相控的电路，该电路采用大容量ＲＯＭ，结构简单，易于实现。     

A classification tool for N-way array based on SIMCA methodology

In the literature there are only few papers concerned with classification methods for multi-way arrays. The most common procedure, by far, is to unfold the multi-way data array into an ordinary matrix and then to apply the traditional multivariate tools for classification. As opposed to unfolding the data several possibilities exist for building classification models more directly based on the multi-way structure of the data. As an example, multi-way partial least squares discriminant analysis has been used as a supervised classification method, another alternative that has been investigated is to perform classification using Fisher's LDA or SIMCA on the score matrix from e.g. a PARAFAC or a Tucker model. Despite a few attempts of applying such multi-way classification approaches, no-one has looked into how such models are best built and implemented.In this work, the SIMCA method is extended to three-way arrays. Included in this work is also actual code that will work on general multi-way arrays rather than just three-way arrays. In analogy with two-way SIMCA, a decomposition model is separately built for the multi-way data for each class, using multi-way decomposition method such as PARAFAC or Tucker3. In the choice of the best class dimensionality, i.e. number of latent factors, both the results of cross-validation but mainly the sensitivity/specificity values are evaluated. In order to estimate the class limits for each class model, orthogonal and score distances are considered, and different statistics are implemented and tested to set confidence limits for these two parameters. Classification performance using different definitions of class boundaries and classification rules, including the use of cross-validated residuals and scores is compared.The proposed N-SIMCA methodology and code, besides simulated data sets of varying dimensionality, has been tested on two case studies, concerning food authentication tasks for typical food products.     

被动免疫算法在模拟电路故障诊断中的应用研究

基于生物免疫系统的信息处理机理,介绍了被动免疫算法的实现过程,并将其应用到某装备电路板的故障诊断之中。该算法具有边检测边学习的动态调整功能,仿真和实验实例表明,该算法适合于电路板的故障诊断,有较高的故障诊断率。     

A built-in self-testing method for embedded multiport memory arrays

With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multiprocessor systems, telecommunication application-specific integrated circuits (ASICs), etc. Research papers which define multiport memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this paper, we develop a powerful test architecture for two-port memories using the serial interfacing technique. Based on the serial testing mechanism, we propose new march algorithms which can prove effective to reduce hardware cost considerably for a chip with many two-port memories. Once we understand how serial interfacing helps test two-port memories, one possible extension is to use serial interfacing for p-port memories (p > 2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead, and tolerable test application time.     

Automated selection of test frequencies for fault diagnosis in analog electronic circuits

This paper suggests three novel methods for selecting the frequencies of sinusoidal test signals to be used in fault diagnosis of analog electronic circuits. The first and second methods are based on a sensitivity analysis and show to be particularly effective in linear circuits where a priori information and designer experience can be exploited. Conversely, the third method selects the input frequencies to be used for diagnostic purposes without requiring any hypothesis about the circuit or testing design background. As such, the method is particularly appealing in complex -possibly nonlinear - circuits where the designer experience is of little value and an effective "blind" approach saves both designer and testing time. The suggested frequency selection methods are then contrasted to each other against performance and computational complexity.     

Sectorised antenna array and measurement methodology for indoor ultra-wideband applications

A new sectorised antenna array (SAA) and measurement methodology are proposed for indoor ultrawideband (UWB) applications. The proposed SAA comprises of one centre element and six side elements. The one centre element and six side elements are arranged in a semi-spherical antenna array configuration. The measurement system and methodology for the coverage of the SAA are developed. The measured bandwidth of the SAA for voltage standing wave ratio (VSWR) <2 is 37.5%, ranging from 3.06 to 4.47 GHz. The boresight gain is more than 5.2 dBi across the impedance bandwidth. The proposed SAA is able to provide omni-directional pattern with an average gain of 5.2 dBi over the angles (0-3608). The discone reference antenna is used to measure the coverage of the proposed SAA. The proposed measurement study shows that the proposed SAA offers omni-directional coverage desirable in UWB indoor location and short-range communication systems.     

A complete scheme of built-in self-tests (BIST) structure for faultdiagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience     

Approach to optimization of metrological support for self-testing automatic measurement systems

A mathematical model for automated measurement systems is proposed. The model provides a basis for specification of self-testing facilities by minimizing the cost of metrological support. Translated from Izmeritel'naya Tekhnika, No. 12, pp. 13–15, December, 1996.     

A general method to perform a noncompetitive immunoassay for small molecules.

A new general method to perform a noncompetitive immunoassay for low-molecular-mass analytes (less than 6000 Da) is described and checked using cortisol as a model system. The method is based on the use of a "polydentate ligand" (cortisol-poly(L-lysine) conjugate) able to block the antibody sites unoccupied by the analyte, followed by the replacement of an antibody-bound analyte by an enzyme-labeled analyte (cortisol-horseradish peroxidase), and permits the direct measurement of the analyte bound sites. The observed signal shows a near-linear correlation with the analyte concentration. The characteristics of interactions between the analyte and polydentate ligand with the specific antibody were studied to perform a preliminary evaluation of the noncompetitive immunoassay for cortisol. The noncompetitive assay was compared with a competitive immunoassay obtained under the same conditions and using the same reagents. The results of the experiments showed a lower detection limit for the noncompetitive model (0.15 ng mL-1 rather than 0.72 ng mL-1), emphasizing that the model is successful. Moreover, as the polydentate ligand is prepared from the same hapten used for the immunogen synthesis, this type of noncompetitive immunoassay appears generally applicable to all small molecules for which antibodies have been obtained.     

Study of the influence of notch radii and temperature on the probability of failure: A methodology to perform a combined assessment

The fracture assessment of notched components based on cracked components approaches leads to over‐conservative failure predictions. In the research literature, several approaches are proposed to overcome this problem using an apparent fracture toughness, . Nevertheless, most of these approaches are based on deterministic assumptions despite the large and variable scatter exhibited by for different notch radii (ρ) or temperatures (T). This paper proposes a methodology for deriving a probabilistic field including the effect of temperature on the failure of notched components. First, the theory of critical distances is applied to transform each apparent fracture toughness into the equivalent fracture toughness for ρ = 0. Then, the temperature is supposed to act as a scale effect in the Weibull cumulative distribution function of the equivalent fracture toughness, and the corresponding scale effect function is derived. Finally, the applicability of the proposed methodology is illustrated by an example using two ferritic‐pearlitic steels: S275JR and S355J2.     

A methodology to control for individual differences in dual-task performance

A study was designed to test the effect of a secondary visual task on a primary visual task. In one condition, participants performed the dual-task, while assigning no weight to the secondary task. In the second condition, the primary task was performed simultaneously with the secondary task. The effect of the added workload was measured via the effect on primary task performance. In the baseline portion of the task, participants had their baseline (90% accuracy) of performance collected by adjusting the stimulus duration. The individual participant stimulus duration was then used as the experimental stimulus duration and the effect of secondary task performance on primary task performance was measured. In a third condition, practice was used as a method of controlling for individual differences. Participants performed the task as in the control condition, however they were given twice as much exposure to the task. Participants ran the study for the full duration twice. Only the performance from the second exposure was collected.     

A simple methodology to visualize crack propagation for ceramic materials

Analysis of the crack growth behavior is critical for fracture and thermal shock assessment. The current work presents a simple methodology to visualize cracks in ceramic materials. The procedure is exemplified for refractory materials on the basis of images obtained during mechanical loading using a wedge splitting test. Complementary in situ crack growth observation verify that for one of the materials growth and opening displacement of the main crack is accompanied by pronounced micro-cracking, branching, and bridging processes. Apparent fracture resistance and thermal shock resistance parameters are discussed.     

一种有效抑制阵列后方声源的心形指向性传声器阵列

基于心形指向性传声器的波束形成可以有效抑制阵列后方声源的干扰,提高前方声源的识别精度。以平面轮形传声器阵列为对象,借助MATLAB仿真计算,对阵列后方声源波束形成声源识别特性及其抑制方法进行研究。基于除自谱的互谱波束形成算法提出了含有传声器指向性的波束形成算法,对圆形和心形指向性传声器进行不同声源类型的波束形成仿真计算,并针对仿真结果显示出的不足,给出了既能保证阵列平面上最大声压贡献量的识别精度,又能降低旁瓣水平的幅值校正算法。试验结果证明了基于心形指向性传声器的波束形成可以有效抑制后方声源。