A burst-error-correcting Viterbi algorithm

A dual-mode burst-error-correcting algorithm that combines maximum-likelihood decoding with a burst detection scheme is presented. The decoder nominally operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. It is demonstrated that the new scheme outperforms interleaving strategies under the constraint of a fixed overall decoding delay. It also proves to be more powerful than known adaptive burst decoding schemes, such as the Gallager burst finding scheme. As the new method can be used with soft decision decoding, it is mainly intended for use on random-error channels affected by occasional severe bursts     

A constraint-length based modified Viterbi algorithm with adaptiveeffort

A modified Viterbi (1971) algorithm for convolutional codes is described that provides for signal-to-noise ratio (SNR) adaptive computational effort. The algorithm has three levels of prioritized effort. Movement from one level to the next is controlled by parameters that can be selected according to desired output bit error rate performance. For 3-bit soft decision detected signals, a coding gain within 0.06 dB of Viterbi at a 3-dB SNR is achieved for the same constraint-length code with modest parameter values and computational effort. At values of SNR above 6 dB, the algorithm decodes with very low computational effort. Effort levels are controlled by spanning the decoding trellis in steps that are one constraint-length long     

A coded ARQ scheme with the generalized Viterbi algorithm

A coded automatic repeat request (ARQ) scheme based on a generalized Viterbi decoding algorithm is proposed. The scheme utilizes the error propagation, which is commonly observed in reduced-complexity decoding, as a means of error detection. It is shown that a small undetectable error probability is obtained with a small retransmission probability for a discrete memoryless channel, contrary to the conventional convolutionally coded ARQ schemes with Viterbi decoding where a compromise between the retransmission probability and the undetectable error probability must be reached     

A new transform algorithm for Viterbi decoding

Implementation of the Viterbi decoding algorithm has attracted a great deal of interest in many applications, but the excessive hardware/time consumption caused by the dynamic and backtracking decoding procedures make it difficult to design efficient VLSI circuits for practical applications. A transform algorithm for maximum-likelihood decoding is derived from trellis coding and Viterbi decoding processes. Dynamic trellis search operations are paralleled and well formulated into a set of simple matrix operations referred to as the Viterbi transform (VT). Based on the VT, the excessive memory accesses and complicated data transfer scheme demanded by the trellis search are eliminated. Efficient VLSI array implementations of the VT have been developed. Long constraint length codes can be decoded by combining the processors as the building blocks     

A personal history of the Viterbi algorithm

This paper describes how Andrew J. Viterbi developed a non-sequential decoding algorithm which proved useful in showing the superiority of convolutional codes over block codes for a given degree of decoding complexity. The Viterbi algorithm is now used in most digital cellular phones and digital satellite receivers as well as in such diverse fields as magnetic recoding, voice recognition, and DNA sequence analysis.     

Efficient Viterbi algorithm for signals with ISI

The authors propose an efficient method of implementing the Viterbi algorithm at Nyquist-rate, for linearly modulated signals corrupted by ISI and AWGN. When signalling is M-ary and ISI extends over L-1 symbols, this scheme results in M+CL (complex multiplications, C is the number of samples per symbol), whereas the whitened-matched-filter based Viterbi algorithm requires M^L complex multiplications     

Implementing the Viterbi algorithm

The Viterbi algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing. It is used to detect signals in communication channels with memory, and to decode sequential error-control codes that are used to enhance the performance of digital communication systems. The Viterbi algorithm is also used in speech and character recognition tasks where the speech signals or characters are modeled by hidden Markov models. The article explains the basics of the Viterbi algorithm as applied to systems in digital communication systems, and speech and character recognition. It also focuses on the operations and the practical memory requirements to implement the Viterbi algorithm in real-time     

A list-type reduced-constraint generalization of the Viterbi algorithm

The Viterbi algorithm (VA), an optimum decoding rule for aQ-ary trellis code of constraint lengthK, operates by taking the best survivor from each ofQ^{K-1}lists of candidates at each decoding step. A generalized VA (GVA) is proposed that makes comparisons on the basis of a label of lengthL(Lleq K). It selects, incorporating the notion of list decoding, theSbest survivors from each ofQ^{L-1}lists of candidates at each decoding step. Coding theorems for a discrete memoryless channel are proved for GVA decoding and shown to be natural generalizations of those for VA decoding. An example of intersymbol interference removal is given to illustrate the practical benefits that the GVA can provide.     

A new architecture for the fast Viterbi algorithm

A novel architecture design to speed up the Viterbi algorithm is proposed. By increasing the number of states in the trellis, the serial operation of a traditional add-compare-select unit is transformed into a parallel operation, thus achieving a substantial speed increase. The proposed architecture would increase the speed by 33% at the expense of a fairly modest increase in area, thus becoming an attractive approach in high-speed applications. A simple example is shown to illustrate the proposed algorithm in maximum-likelihood sequence detector. A comparative synthesis is made to compare the proposed architecture with other approaches, and synthesis simulations confirm the projection of the throughput gain. Also, the proposed algorithm is extended to the block-processing architecture, and we show that an additional 50% speedup is achieved.     

Contributions to the application of the Viterbi algorithm

The Viterbi algorithm is an efficient technique to estimate the state sequence of a discrete-time finite-state Markov process in the presence of memoryless noise. This work sets up a relationship to a general class of linear and nonlinear fast algorithms such as FFT, FWT, and optimal sorting. The performance of a Viterbi detector is a function of the minimum distance between signals in the observation space of the estimated Markov process. It is shown that this distance may efficiently be calculated with dynamic programming using a slightly modified Viterbi algorithm of an increased basis.     

Performance degradation of Viterbi algorithm with reduced cost

The cost of the Viterbi algorithm increases exponentially with the constraint length m, a fact which restricts practical applications to small values of m. Cost can be reduced substantially by restricting either the metric or the number of states. Simulation results show the trade-off between cost reduction and performance     

联合判决估计的Viterbi译码算法

利用相邻几组判决数据之间的相互关系，对这几组数据进行联合判决估计，从而提两了Viterbi译码性能。从理论分析和仿真结果来看，当译码深度τ=2m左右时，译码性能相当于深度2τ传统算法的性能。此外，仿真表明参考状态的位置对性能影响不大。因此该算法在保证同等性能前提下，对留选路径存储的规模和功耗减少约20％，对回溯单元减少达30％。     

On the Viterbi decoding algorithm

A new interpretation of the Viterbi decoding algorithm based on the state-space approach to dyamical systems is presented. In this interpretation the optimum decoder solves a generalized regulator control problem by dynamic programming techniques.     

Application of the Viterbi algorithm to adaptive delta modulation with delayed decision

The Viterbi algorithm is applied to adaptive delta modulation with delayed decision. The resulting coder is more efficient, while the search time involved is reduced by a factor equal to the decision delay expressed in input pulse epochs.     

Viterbi decoding algorithm for convolutional codes with repeat request

Using the Viterbi decoding algorithm with repeat request for convolutional codes is proposed, and the resulting performance is analyzed by random coding and generating function arguments and by simulation. It is shown that the reliability function of the proposed decoding algorithm is asymptotically twice that of the Viterbi decoding algorithm without repeat request, and that in certain practical situations the proposed algorithm can save about 50 percent in constraint length over the ordinary Viterbi algorithm for a given performance.     

Adaptive Viterbi algorithm with ARQ for bounded complexity decoding

Adaptive bounded computational and memory requirements for a Viterbi decoder can be achieved using an error trapping Viterbi decoder algorithm initially develop for hybrid automatic repeat request (ARQ) implementations. Partial path metrics and a sliding window are used to eliminate unreliable paths in the decoder trellis thus reducing the computational and memory requirements. An ARQ is issued if all paths are eliminated. The algorithm is adaptive allowing the receiver to dynamically allocate memory and processing, to improve reliability or received packets, or to reject packets with lower reliability to avoid buffer overruns. The result is the ability to trade off resources versus delay and throughput.     

Iterative Viterbi algorithm: implementation issues

We address several issues for implementing the iterative Viterbi decoder. We show that 3-bit branch metric quantization, 7- or 8-bit state metric precision, and a survivor length of five times the constraint length yields little degradation for the iterative Viterbi algorithm (IVA). Our results show that without changing the VA hardware (except adding some additional circuits), the error performance of several standard systems can be significantly improved.     

The Viterbi algorithm for sparse channels

This paper presents a reduced complexity Viterbi algorithm for use as sequence estimator for linear intersymbol interference channels with coarsely located coefficients. In particular, the complexity does not depend on the channel impulse response length but only on the number of nonzero coefficients. No approximations are used in the algorithm. We consider a multipath environment producing time spreads     

Viterbi algorithm with data-aided phase reference estimation forconvolutionally encoded PSK

A Viterbi algorithm with data-aided phase reference estimation for convolutionally encoded PSK is presented. The simulated error performance results are given. Very attractive results are obtained, which show that the new Viterbi algorithm with data-aided phase reference estimation can provide almost the same performance as that of the Viterbi algorithm with perfect phase reference     

High-performance VLSI architecture for the Viterbi algorithm

The Viterbi (1967) algorithm (VA) is known to be an efficient method for the realization of maximum-likelihood (ML) decoding of convolutional codes. The VA is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. We present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated, optimizing the use of the PEs and the communications. Therefore, the algorithm is mapped onto a column of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints. Furthermore, the management of the surviving path memory for its mapping and distribution among the processors was studied. As a result, we obtain a regular and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data recirculations between stages