Advanced constant multiplier for multipath pipelined FFT processor

A novel method for reducing the number of equivalent complex multipliers for a multipath mixed-radix 128-point FFT processor using an advanced constant multiplier is proposed.     

Memoryless pipelined trigonometric processor

The development and results of memoryless algorithms for the evaluation of sinusoidal functions are described. Differing from the MacLaurin power series method, the algorithms proposed here use the binary representation of an angle in a pipelined manner to calculate sinusoidal functions.<>     

An architecture for a VLSI FFT processor

We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI.     

Dynamically scalable dual-core pipelined processor

This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs. This design aimed to be implemented on Xilinx Spartan 3E XC3S500E FPGA.     

Area-efficient FPGA-based FFT processor

A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the 'twiddle factors' sequentially leads to an area saving up to 35% with respect to other cores.     

An efficient pipelined architecture for real-valued Fast Fourier Transform

Real-valued Fast Fourier Transform (FFT) plays an important role in today’s digital world because of the fact that most of the signals contain real values. The FFT computation of real signals using conventional techniques requires more hardware space with high power consumption, which is the most important task for a researcher while designing VLSI architectures. This can be eradicated by clearly analysing the symmetric property of the real-valued signals. In this paper, we have adopted the symmetric property and designed an efficient pipelined architecture for 16-point DIF FFT. The pipeline scheme reduce the processing time at the cost of some registers and in order to contribute efficiently for power reduction we have modified the complex multiplier with reduced internal real multipliers which are in turn replaced by an modified canonic signed digit multiplier (CSDM) with resource-sharing technique. The complete module is synthesised and simulated using Xilinx ISE 14.1 with the target device is Virtex-5 xc5vlx110T. The experimental results verify that our implemented design is more efficient in terms of speed, area and power when comparing with similar works.     

基于FPGA的FFT处理器设计

针对快速傅里叶变换（FFT）算法的结构和特点,提出了一种基于现场可编程门阵列（FPGA）设计FFT运算的方案。该方案采用基2算法以及单元结构的设计思路,对FFT处理器合理模块化,用VHDL语言对各个模块编程,并在Quartusll软件环境下综合仿真,时序分析结果与Matlab计算结果相一致验证了设计的正确性。FFT与FPGA相结合提高了运算速度,扩大了FFT的应用领域。     

A digital processor for full calibration of pipelined ADCs

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC.     

FFT复数处理器设计与FPGA验证

本文介绍了一种基于现场可编程门阵列(FPGA)的快速傅里叶变换(FFT)复数处理器设计,可进行1024点复数计算。采用按时间抽取的基-4算法和基于RAM的蝶形结构。同时对最后一级旋转因子进行了优化,减少了存储器的资源占用。使用流水线的处理结构,控制器简单。最后定点matlab建模与Synopsys的仿真器VCS仿真结果进行了对比,功能正确。完成整个运算仅用了2064个周期。最后用Altera公司的CycloneIVE系列EP4CE10E22C8芯片完成原型验证,在时钟频率为50MHz时,完成1024点复数FFT仅用41.28μs。     

3780点FFT处理器的研究

3780点FFT模块是地面数字多媒体／电视广播传播系统（DMB—T）中的重要模块之一，由于该模块不能直接利用现已成熟的基-2和基-4的算法，故给出了三种实现3780点FFT的算法和处理器结构，分别是内插成4096点的FFT算法、混合基FFT算法和综合分解算法，并对各种方法的优缺点进行了讨论。     

基于CORDIC的FFT处理器设计

波束形成是阵列信号处理过程的一个重要步骤,它在雷达、地质勘探、医学成像领域起着关键的作用并得到了广泛的应用。在声呐系统中,FFT处理器是波束形成器的关键部件,论文中引用了CORDIC算法,并对比了基2、基4等时域FFT算法的区别,根据基本原理和流程最终选定了基4算法,将其有效地和CORDIC算法结合起来。设计了一款基于CORDIC算法的FFT处理器。采用流水线方式,形成了5级蝶形算法,满足了FFT运算要求。     

A radix-8 wafer scale FFT processor

Wafer Scale Integration promises radical improvements in the performance of digital signal processing systems. This paper describes the design of a radix-8 systolic (pipeline) fast Fourier transform processor for implementation with wafer scale integration. By the use of the radix-8 FFT butterfly wafer that is currently under development, continuous data rates of 160 MSPS are anticipated for FFTs of up to 4096 points with 16-bit fixed point data.     

一种面向多核处理器高效并行的Montgomery加密算法

经典 Montgomery 阶梯算法是提高椭圆曲线加密运算效率的有效方法之一。首先利用循环展开技术,提出了一种改进的 Montgomery 阶梯算法。然后根据 Montgomery 椭圆曲线加密算法的特点,在其读入数据环节采取数据并行方式进行处理;在其模幂运算环节采取任务并行方式进行处理。仿真实验结果表明,采用数据并行和任务并行2种方式,可有效提升椭圆曲线加密运算的效率。     

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single-instruction multiple-data (SIMD) unit designed to accelerate media and data streaming with 128-bit operands. It supports 32-bit single-precision floating-point and 16-bit integer operands with two different latencies, six-cycle and seven-cycle, with 11 FO4 delay per stage. The FPU optimizes the performance of critical single-precision multiply-add operations. Since exact rounding, exceptions, and de-norm number handling are not important to multimedia applications, IEEE correctness on the single-precision floating-point numbers is sacrificed for performance and simple design. It employs fine-grained clock gating for power saving. The design has 768K transistors in 1.3 mm/sup 2/, fabricated SOI in 90-nm technology. Correct operations have been observed up to 5.6 GHz with 1.4 V and 56/spl deg/C, delivering 44.8 GFlops. Architecture, logic, circuits, and integration are codesigned to meet the performance, power, and area goals.     

Radix-2 FFT butterfly processor using distributed arithmetic

A parallel-data VLSI architecture for computation of the fast Fourier transform (FFT) is described. The processor is based on a computationally efficient vector rotate algorithm. Use of a 2-dimensional pipeline configuration allows a radix-2 butterfly operation to be performed once every system clock cycle (250 ns) to generate real or imaginary transform components. The architecture is considered to be a computationally efficient VLSI approach for high-bandwidth computation of the FFT. The design and performance of an 8-bit FFT butterfly processor are described.     

A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.<>     

A dynamic scaling FFT processor for DVB-T applications

This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-/spl mu/m single-poly six-metal CMOS process with core area of 4.84 mm/sup 2/. Power dissipation is about 25.2 mW at 20 MHz.     

A VLSI array processor for 16-point FFT

An implementation of a two-dimensional array processor for fast Fourier transform (FFT) using a 2-μm CMOS technology is presented. The array processor, which is dedicated to 16-point FFT, implements a 4×4 mesh array of 16 processing elements (PEs) working in parallel. Design considerations in both the chip level and the PE level are examined. A layout design methodology based on bit-slice units (BSUs) results in a very simple design, easy debugging, and a regular interconnection scheme through abutment. It contains about 48,000 transistors on an area of 53.52 mm², excluding the 83-pad area, and operation is on a 15-MHz clock. The array processor performs 24.6 million complex multiplications per second, and computes a 16-point FFT in 3 μs