低插入损耗高隔离度SOI射频开关电路的研究

基于0.18μm RF SOI CMOS工艺,提出了一种可广泛应用于无线通信系统中的低插入损耗高隔离度SOI射频开关电路.该电路利用SOI器件的特殊结构(隐埋氧化层BOX,高阻衬底)和特殊SOI器件(FB,BC,BT等),使电路采用的器件较之体硅CMOS器件具有更优的隔离性能,实现了降低插入损耗和增加隔离度的目的.该电路经过模拟仿真,在频率为2.4 GHz时,插入损耗和隔离度分别为-1 dB和40 dB.     

基于SOI衬底的射频电感优化设计

比较了SOI RF电感与体硅电感的性能,并根据模拟结果分析了电感中空面积,电感形状结构,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响,最后提出了一种基于SOI衬底RF电感的优化设计原则.以往射频集成电感性能的比较并不固定电感值,而文中全部参数的变化都是在电感值相同的情况下进行比较.     

射频SOI LDMOS功率放大器设计与仿真

简介了改进的绝缘层上硅横向扩散金属氧化物一半导体(SOI LDMOS)电路模型.根据改进的SOI LDMOS电路模型,采用射频仿真软件进行了射频功率放大器的设计与仿真.该射频功率放大器采用两级放大结构,采用了S参数设计方法和负载牵引方法设计.结果表明放大器的增益达到15 dB,输出功率达到25 dBm,功率附加效率大于40%.     

RFSOICMOS技术及其应用

介绍了RF SOI CMOS技术的特点。着重论述了RF SOI CMOS技术的低串扰特性、低损耗特性及其优质无源元件的性能。最后,阐述了RF SOI CMOS技术在RF系统片上集成方面的应用情况。     

基于MEMS的矩形微同轴技术研究现状

矩形微同轴技术已成为射频微电子机械系统(RF MEMS)的一个重要发展方向。矩形微同轴的电性能相比于传统的传输结构(如微带、共面波导等)在毫米波宽带领域具有巨大优势。从结构、性能等方面对矩形微同轴进行了简要分析。回顾了矩形微同轴技术在其发展的不同阶段出现的体硅刻蚀技术、EFABTM和PolyStrataTM技术,并对矩形微同轴的结构、加工工艺及射频性能等方面进行了简要分析。介绍了矩形微同轴技术在不同RF MEMS中的应用,并对获得的特性进行了讨论。矩形微同轴技术应用于高度集成的RF MEMS是发展的必然趋势,必将对传统射频电路的设计、制备及系统集成产生巨大影响。     

基于RF MEMS开关的新型双频带功率放大器

RF MEMS开关具有低损耗、低功耗、尺寸小和易于集成等优点而被广泛应用于各种可重构射频电路及系统中。通过分析比较电容并联式和串联式RF MEMS开关两种电路结构的射频性能,设计了一种基于RF MEMS开关的新型功率放大器,使用RF MEMS开关控制匹配网络来实现双工作频带的转换。结果表明,设计的功率放大器在2.35GHz和1.25GHz两个工作频带下,功率附加效率(PAE)和输出功率(Pout)可分别达到72%、67%及40.8、42.7dBm。该功率放大器具有较高的功率附加效率和输出功率,适用于多频带的射频系统,对RF MEMS器件在可重构系统中的应用具有一定参考价值。     

华虹半导体推出0.2微米射频SOI工艺设计工具包

华虹半导体有限公司推出全新的0.2微米射频SOI(绝缘体上硅)工艺设计工具包(Process Design Kit,PDK)。这标志着新的0.2微米射频SOI工艺平台已成功通过验证,并正式投入供客户设计开发使用。工艺设计工具包(PDK)的推出可协助客户快速完成高质量射频器件的设计与流片。华虹半导体的0.2微米SOI工艺平台是专为无线射频前端开关应用优化的工艺解决方案。相比基于砷化镓(Ga As)和蓝宝石(SOS)衬底的射频开关设计,SOI可以使客户在获得优秀性能和扩展能力的     

基于SOI衬底的射频电感优化设计

比较了SOIRF电感与体硅电感的性能 ,并根据模拟结果分析了电感中空面积 ,电感形状结构 ,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响 ,最后提出了一种基于SOI衬底RF电感的优化设计原则 .以往射频集成电感性能的比较并不固定电感值 ,而文中全部参数的变化都是在电感值相同的情况下进行比较     

改性离子注入高阻SOI衬底的共面波导特性研究

因良好的射频性能,高阻SOI(High-Resistivity Silicon-on-Insulator,HR-SOI)被广泛应用于射频集成电路(RFICs)。通过提取共面波导传输线(Co-Plane Waveguide,CPW)的射频损耗来表征衬底材料的射频性能。高阻SOI衬底由于表面寄生电导效应(Parasitic Surface Conductance,PSC),射频性能恶化。设计并制备了一种新型的改性结构来优化高阻SOI的射频性能,通过将硅离子注入到绝缘埋层中来消除表面寄生电导效应。在0~8 GHz范围内,传输线损耗优于时下业界最先进的TR-SOI的结果(Trap-Rich Layer Silicon-on-Insulator)。由于工艺简单,易于集成化,是极具潜力的射频SOI材料。     

0．8μm SOI CMOS技术及电路研制

SOI CMOS技术在一些特殊应用领域中有着体硅无法比拟的优势文中叙述采用SIMOX材料和0.8μm SOI CMOS工艺加固技术成功研制出抗辐射性能较好的器件和电路,并且给出了SOI CMOS器件的特性随辐照总剂量的变化关系,试验电路通过了总剂量500 Krad(Si)钴60γ射线辐照实验。     

SOI CMOS模拟集成电路发展概述

从SOI CMOS模拟集成电路(IC)中存在的关键问题——浮体效应——及其影响出发，介绍了在解决浮体效应以后，已实现的有代表性的模拟集成电路的发展状况。特别指出了SOI CMOS在实现RF电路及SOC芯片中的优点。     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Investigation of a multigigahertz MOSFET amplifier with an on-chipinductor fabricated on a SIMOX wafer

This paper describes a technology that can be used to integrate multigigahertz RF circuits into large-scale digital circuits. Spiral inductors and a MOSFET amplifier with an inductive load were fabricated on a SIMOX wafer in order to demonstrate the feasibility of SOI technology. With a 1-V supply voltage, peaking of the amplifier gain was observed, as expected from circuit simulations, at 1-4 GHz. These results show that RF circuits with inductors can be implemented on a SIMOX wafer by using the conventional digital CMOS LSI process     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

太赫兹倍频器研究进展

太赫兹CMOS电路具有小型化、与大规模硅基工艺兼容的特点,非常适合未来太赫兹通信以及5G通信的应用。本文以太赫兹CMOS本振电路为切入点,调研了国际和国内的最新CMOS倍频器电路结构,在此基础上,对推推(push-push)倍频器、注入锁定倍频器以及混频倍频器的电路结构和特点进行了详细介绍。通过对以上几种倍频器的分析对比,总结了不同的倍频器在实际应用中的优缺点,为太赫兹射频前端小型化实际应用奠定基础。     

SOI技术的机遇和挑战

本文较为系统地描述了SOI技术的特点,分析了SOI技术中存在的问题和发展的潜力,最后得出了SOI技术将在特征尺寸小于0．1um,电源电压小于1V的新一代集成电路技术中得到了广泛应用。     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Stacked CMOS circuits integrated in laser-recrystallized silicon films

Laser-recrystallized poly-silicon films are used as a substrate for the integration of MOS transistors and CMOS circuits. Ring oscillators and frequency divider circuits up to 100 transistors operate well with a yield of about 80%. For the integration of stacked CMOS circuits already tested bulk structures are covered with a dielectric layer and a poly-silicon film which is recrystallized at low temperature. The SOI integration technique, with a maximum temperature treatment of 960°C, is employed to manufacture the second active area as a 3-D technology. After the integration process SOI and bulk CMOS transistors operate independently at two different active levels.     

Transient drain current and propagation delay in SOI CMOS

The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO2) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.     

Integrated sensor and electronic circuits in fully depleted SOItechnology for high-temperature applications

The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300°C