Digital computation of frequency response of multiloop systems

An application-oriented program is described for the digital computation of the frequency response of linear multiloop systems. The main advantage of the program lies in the extreme simplicity of the data requirements and the consequent ease of application. Apart from the values of the parameters of the individual transfer functions comprising the overall system, the only other data required are a very simple and concise instruction array. The program has application in control-system design, compensation and stability analysis.     

集成循环代码cache降低微控制器功耗研究

功耗对于面向低成本低功耗应用的微控制器(单片机)十分重要.研究表明,CPU由于取指对程序存储器的访问功耗,构成了微控制器整体功耗的重要组成部分,而微控制器应用程序的大部分执行时间被用于执行固定的循环代码.研究了集成循环代码cache,从中执行循环代码来降低存储器访问功耗的技术.     

A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability

A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million instructions per second and up to six concurrent operations in each instruction. Two DSPs, the PCB5010 and PCB5011, have been developed. Both are based on a common architecture which contains two 16-bit data buses, and a 16/spl times/16/spl rarr/40-bit multiplier accumulator and 16-bit ALU, both with multiprecision support in hardware. Also implemented are two static data RAMs (128/spl times/16 or 256/spl times/16), a data ROM (51/spl times/16), a 15-word three-port register file, three address computation units, and five serial and parallel I/O interfaces. The data path is controlled by an orthogonal instruction set, using 40-bit microcode words. The controller contains a five-level stack and an instruction repeat register, and can have either on-chip program memory (RAM: 32/spl times/40; ROM: 987/spl times/40) or off-chip program memory (up to 64K/spl times/40). Benchmarks show a two to sixfold improvement in overall performance over its predecessors.     

基于控制流的混合指令预取

取指令能力的高低对微处理器的性能有很大影响.指令预取技术能够有效地降低指令Cache的访问失效率,提高微处理器的取指令能力,进而提高微处理器的性能.本文提出了一种基于程序控制流的混合指令预取机制,它采用顺序预取和非顺序预取相结合的方式将指令提前读入指令Cache.模拟结果显示,该方法能够有效地提高指令Cache访问的命中率,并具有实现简单,无效预取率低等特点.     

基于软硬件协同仿真平台的功能仿真测试方法

针对数字信号处理器的不同仿真测试要求，提出了基于软硬件协同仿真平台的功能仿真测试方法。采用软硬件协同仿真测试的方法，提高了被测处理器的仿真测试速度；采用基于指令模型的指令集测试程序，提高了基本指令集的测试覆盖率；采用基于流水控制单元状态机变换路径的测试程序，提高了指令间数据竞争的检测。实验结果表明，指令的覆盖率达到了100％，且DSP处理器代码的覆盖率也达到了满意的程度。     

A Computer-Aided Multisensory Instruction System for the Blind

A multisensory conversational learning facility is described which permits the visually handicapped to share the process and content of instruction of sighted persons. The blind student receives live or recorded audio and graphic instruction synchronously via his aural and tactile/kinesthetic senses. A novel kinesthetic terminal for the blind is described which permits ``visual' perception of kinetic graphics. In the classroom the blind student perceives blackboard graphics concurrently with the instructor's live presentation; in the self-instruction mode he connects to a remote bank of audiographic instructional materials and receives lessons via telephone through a combined audio/kinesthetic terminal. The conversational learning system which serves simultaneously varying numbers of blind and sighted learners is controlled by a mini-computer. Applications of the audio/kinesthetic terminal in education of sighted persons and in research on information processes of the blind are briefly noted.     

Architecture and design of a 500-MHz gallium-arsenide processingelement for a parallel supercomputer

The design of the processing element of GASP, a GaAs supercomputer with a 500-MHz instruction issue rate and 1-GHz subsystem clocks, is presented. The novel, functionally modular, block data flow architecture of GASP is described. The architecture and design of a GASP processing element is then presented. The processing element (PE) is implemented in a hybrid semiconductor module with 152 custom GaAs ICs of eight different types. The effects of the implementation technology on both the system-level architecture and the PE design are discussed. SPICE simulations indicate that parts of the PE are capable of being clocked at 1 GHz, while the rest of the PE uses a 500-MHz clock. The architecture utilizes data flow techniques at a program block level, which allows efficient execution of parallel programs while maintaining reasonably good performance on sequential programs. A simulation study of the architecture indicates that an instruction execution rate of over 30,000 MIPS can be attained with 65 PEs     

基于PLC的模拟量闭环控制系统PID的实现

文章对模拟闭环控制系统的原理、变送器的选择方法及闭环控制系统主要性能指标进行了描述,介绍了PID控制器的数字化过程及PID指令向导生成PID程序的步骤,通过S7-200 SMART PLC编程实现该控制过程,并进行了参数整定,达到了控制效果。     

一种DSP程序控制结构的分析

DSP程序控制是DSP指令执行控制的核心和关键。文章通过分析DSP程序控制的流程及其实现方式,详细阐述了程序控制所需的程序计数器、堆栈及程序重复计数器等关键逻辑部件工作原理及其作用。实现了一种程序控制中的加减运算逻辑,揭示了指令执行中各程序地址的加载关系,为实现DSP程序控制逻辑的设计提供了一种参考方法。     

Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory

Bit faults induced by single-event upsets in instruction may not cause a system to experience an error. The instruction vulnerability factor (IVF) is first defined to quantify the effect of non-effective upsets on program reliability in this paper; and the mean time to failure (MTTF) model of program memory is then derived based on IVF. Further analysis of MTTF model concludes that the MTTF of program memory using error correcting code (ECC) and scrubbing is not always better than unhardened program memory. The constraints that should be met upon utilizing ECC and scrubbing in program memory are presented for the first time, to the best of authors’ knowledge. Additionally, the proposed models and conclusions are validated by Monte Carlo simulations in MATLAB. These results show that the proposed models have a good accuracy and their margin of error is less than 3 % compared with MATLAB simulation results. It should be highlighted that our conclusions may be used to contribute to selecting the optimal fault-tolerant technique to harden the program memory.     

嵌入式处理器中SDRAM控制器的指令FIFO设计及优化

本文提出了SDRAM预取FIFO的设计，充分利用SDRAM的流水特性，提高无Cache嵌入式处理器性能。通过软件指令静态分析和软件模拟两种分析方法，评估预取逻辑的深度，得到最优化的设计。基于Drystone基准程序的测试表明，本文提出的指令FIFO可以将处理器的性能提高约50％。     

A Framework for Power-Gating Functional Units in Embedded Microprocessors

Power gating is a technique commonly used for leakage reduction in integrated circuits. In microprocessors, power gating is implemented by using sleep transistors to selectively deactivate circuit modules that remain idle for sustained periods of time during program execution. In this work, we develop a new framework for power gating the functional units in embedded system microprocessors without degradation in performance. The proposed framework includes an efficient algorithm for idle time estimation, appropriate insertion of sleep instructions within the code, and a method for reactivating the sleeping units only when needed without the use of wakeup instructions. We introduce the notion of loop hierarchy trees (LHTs) to represent the partial ordering of the nested loops within the program. From the control flow graph (CFG) representation of the source program, a forest of LHTs is constructed and is used to identify the maximal subgraphs representing the long idle periods for the functional units. For each subgraph thus identified, a sleep instruction is introduced in the program with a list of corresponding functional units to be deactivated. When an instruction is decoded, the functional units needed for that instruction are automatically activated by the control unit such that the units are ready before the instruction reaches the execute stage. This eliminates the need for wakeup instructions to be inserted into the object code reducing the overheads. In our implementation, the ARM processor architecture was modified and resynthesized to include power gating by developing a CMOS cell library of functional units with the above capabilities. Experimental results are reported for a set of 12 benchmarks chosen from the MiBench suite, which indicate that, on average, our technique reduces the leakage energy in functional units by 31.1% for integer benchmarks and 26.8% for floating-point benchmarks.     

Instruction set independent program encoding

Instruction encoding techniques have been designed for reducing the program memory footprint and improving processors performance. However, many techniques are instruction-set dependent thus minimizing the adoption in different application domains and target processors. This paper presents an instruction encoding technique and a software framework tool for the design of instruction encoders independent of the instruction set. Our approach is based on (1) a methodological extension of a pattern based instruction word (PBIW) algorithm for instruction encoding; (2) the design and implementation of a software framework for minimizing the design time frame of different instruction encoding algorithms; (3) a comprehensive set of experiments showing the impacts of those techniques on memory footprint, program performance, and processor design. Our proposed framework has been used to encode a wide range of programs compiled for the \(\rho \)-VEX and SPARCv8 instruction sets. The experiments show that the framework makes it able to match the PBIW encoding technique to different ISAs and target machines. The results with SPECint00, Media, MiBench, and simple benchmarks show a compression ratio up to 0.54 (46 % of size reduction) for PBIW-SPARC programs and up to 0.59 for PBIW-VEX programs. Encoded SPARC programs have a performance speedup up to 1.7 compared to non-encoded SPARC programs.     

“微纳机电系统”课程教学方法探讨

本文从"微纳机电系统"课程的内容特点与教学方式两个方面对其教法展开了探索性研究。在课程内容方面,我们讨论了物理模型理解在该课程中的作用,强调了点面结合,系统地介绍微纳加工工艺的重要性。在教学方式上,我们增加建模软件ANSYS上机练习,提高学生的动手能力;结合工程实际问题,系统地介绍某一经典器件。     

An Error Detection Model for Application During Software Development

A variation of the Jelinski/Moranda model is described. The main feature of this new model is that the variable (growing) size of a developing program is accommodated, so that the quality of a program can be estimated by analyzing an initial segment of the written code. Two parameters are estimated from the data. The data are: a) time separations between error detections, b) the number of errors per written instruction, c)the failure rate (or finding rate) of a single error, and d) a time record of the number of instructions under test. This model permits predictions of MTTF and error content of any software package which is homogenous with respect to its complexity (error making/finding). It assists in determining the quality, as measured by error contents, early on, and could eliminate the present practice of applying models to the wrong regimes (decreasing failure rate models applied to growing-in-size software packages). The growth model is very tractable analytically. The important requirement for applications is that the error-making rate must be constant across the entire software program.     

Exploiting statistical information for implementation of instruction scratchpad memory in embedded system

A method to both reduce energy and improve performance in a processor-based embedded system is described in this paper. Comprising of a scratchpad memory instead of an instruction cache, the target system dynamically (at runtime) copies into the scratchpad code segments that are determined to be beneficial (in terms of energy efficiency and/or speed) to execute from the scratchpad. We develop a heuristic algorithm to select such code segments based on a metric, called concomitance. Concomitance is derived from the temporal relationships of instructions. A hardware controller is designed and implemented for managing the scratchpad memory. Strategically placed custom instructions in the program inform the hardware controller when to copy instructions from the main memory to the scratchpad. A novel heuristic algorithm is implemented for determining locations within the program where to insert these custom instructions. For a set of realistic benchmarks, experimental results indicate the method uses 41.9% lower energy (on average) and improves performance by 40.0% (on average) when compared to a traditional cache system which is identical in size.     

Opcode encoding for low-power instruction fetch

A method for encoding opcodes for low-power instruction fetching is described. To reduce the switching activity from opcode changes in the instruction fetch logic, opcodes are assigned so that more frequently consecutive instruction pairs have a smaller Hamming distance between their opcodes. The experimental result shows that a switching activity reduction of 37.4-66.7% is achievable over a naive encoding method     

Microwave education in Belgium

The author points out that in Belgium, a small country with 10 million inhabitants in a 30000 km² area, engineering education is provided by seven universities and a military school in a five-year program, as well as by a limited number of schools in a four-year program. Microwave education within the universities is described. The link between research and education is emphasized, showing similarities and differences among the various centers of education. Specific microwave design expertise, capabilities, and facilities are described     

基于HMM的微控制器旁路模板指令序列恢复

针对微控制器代码旁路逆向恢复的问题,采用逆向工程思想与旁路攻击方法,依据不同的指令在芯片内执行时,会产生不同的功耗旁路泄漏信号这一特点,在已实现的单条指令旁路模板恢复的基础上,综合考虑程序的"上下文"信息,运用隐马尔可夫模型(HMM)对该问题进行建模描述与求解.对AT89C52微控制器中运行的数据加密标准(DES)加密算法的部分指令序列的恢复实验表明,该方法能够有效的恢复出微控制器芯片中运行的指令序列.