Fuzzy logic architecture using subthreshold analogue floating-gatedevices

A subthreshold fuzzy logic architecture is proposed which includes floating-gate devices acting as nonvolatile analogue memories. The use of floating-gate devices which are embedded within the architecture reduces the size and power consumption of the system. Using the proposed subcircuits, a system containing 75 rules can be implemented in less than 5 mm² while consuming 500 μW. The system is, therefore, suitable for integration within a smart sensor, an application area in which low-power consumption and compactness are potentially critical     

基于单逻辑程序的一致性规划任务有限域表示方法

有限域表示(FDR)能有效地压缩状态空间, 其转换算法在实例化阶段对每个初始状态都生成一个逻辑程序, 而一致性规划任务的初始状态数量通常较大, 所以这通常需要较大的时间和空间开销, 甚至导致内存溢出。为了提高转换算法运行效率使其能处理更为复杂的规划问题, 提出了一种基于单逻辑程序的IFDR转换算法。IFDR算法从初始信念状态中所有可能的初始世界状态得到一个事实集, 再由动作和公理计算得到一个规则集。一个事实集和一个规则集组成一个逻辑程序, IFDR用此单逻辑程序完成实例化。实验结果表明IFDR算法在解决问题的效率和数量上都有所提高。     

Nonlinear waveform generation

We developed three analog logic SPICE (Simulation Program with Integrated Circuit Emphasis, developed at the University of California, Berkeley, CA) subcircuits, a voltage comparator and a nonlinear waveform generator to compliment the previously derived functions (Goldstein and Rypins, Comput. Methods Programs Biomed. 29 (1989) 161-172) that simplify modeling of physiologic systems. The logic elements are the 'AND', 'OR' and 'NOT' Boolean functions. In addition, we derived a voltage comparator for use in our composite waveform generator. All the circuits are analog so they can be incorporated into existing analog circuits while performing digital functions.     

Comparative semantics for flow of control in logic programming without logic

We study semantic issues concerning control flow notions in logic programming languages by exploring a two-stage approach. The first considers solely uninterpreted (or schematic) elementary actions, rather than operations such as unification, substitution generation, or refutation. Accordingly, logic is absent at this first stage. We provide a comparative survey of the semantics of a variety of control flow notions in (uninterpreted) logic programming languages including notions such as don't know versus don't care nondeterminism, the cut operator, and/or parallel logic programming, and the commit operator. In all cases considered, we develop operational and denotational models, and prove their equivalence. A central tool both in the definitions and in the equivalence proofs is Banach's theorem on (the uniqueness of) fixed points of contracting functions on complete metric spaces. The second stage of the approach proceeds by interpreting the elementary actions, first as arbitrary state transformations, and next by suitably instantiating the sets of states and of state transformations (and by articulating the way in which a logic program determines a set of recursive procedure declarations). The paper concentrates on the first stage. For the second stage, only a few hints are included. Furthermore, references to papers which supply details for the languages PROLOG and CONCURRENT PROLOG are provided.     

Constructing self-testing circuits with the use of step-by-step (cascade) control

A method of control is proposed on the basis of representing the checked circuits as consequently connected subcircuits (cascades). The subdivision of the circuits into cascades is made in such a way that any failure in each of them results in a distortion of no more than one binary digit at its input. There is developed an universal sequential-sampling circuit with step-by-step control, where the detection of errors does not require additional (coding) variables. The results of this investigation showed that the proposed method for operational control entails considerably lesser hardware and power expenditure as compared with the circuits based on application of the Berger code.     

智能规划的逻辑编码方式研究

逻辑编码方式的设计和实现是基于转换的规划方法有效处理的关键.对几种智能规划方法中的逻辑编码方式予以分析,分别介绍线性编码、基于Graphplan的编码、基于状态的编码、基于动作的编码、基于命题的编码、基于转移的编码、提升的因果编码、基于多值变元的编码、基于有向二元决策图的编码以及基于约束可满足的编码等,并结合国际规划竞赛和相关论文等的实验结论,说明上述编码方式的有效性和可行性,分析该类编码方式在其他领域的应用前景.最后,提出目前智能规划方法中逻辑编码方式研究所面临的挑战、可能的处理方法,以及与之相关的研究热点与趋势.     

Saving Space by Fully Exploiting Invisible Transitions

Checking that a given finite state program satisfies a linear temporal logic property suffers from the state explosion problem. Often the resulting lack of available memory is more significant than any time limitations. One way to cope with this is to reduce the state graph used for model checking. We present an algorithm for constructing a state graph that is a projection of the program's state graph. The algorithm maintains the transitions and states that affect the truth of the property to be checked. Especially in conjunction with known partial order reduction algorithms, we show a substantial reduction in memory over using partial order methods alone, both in the precomputation stage, and in the result presented to a model checker. The price of the space reduction is a single additional traversal of the graph obtained with partial order reduction. As part of our space-saving methods, we present a new way to exploit Holzmann's Bit Hash Table, which assists us in solving the revisiting problem.     

LOMACH — a MOS circuit mask checking logic simulator

Logic simulators were originally developed for logic diagram verification. Their use for mask verification is a complex task of logic diagram recognition based on the information gained from masks to be made. The simulator LOMACH is based on the idea that logic states do not propagate through the nodes of a logic diagram but rather through diffusion regions defined directly by the masks. This paper provides postulates governing the logic state wave propagation, and suggests an internal database and algorithms for checking topological correctness and logic function simulation.     

从命题逻辑的需求描述到状态转移图的形式规格

信息处理系统的规模和复杂化,需要有效设计高可靠性系统的形式化的规模描述方法,本文针对以上功能,提出了基于命题逻辑的信息处理系统的新的需求描述方法,描述了通过使用逻辑ＰｅｔｒｉＮｅｔ（ＬＰＮ）,把命题逻辑的需求描述变换成状态转移图的过程,并且给出了由ＬＰＮ自动生成状态的转换图的算法。     

A Partial Order Approach to Branching Time Logic Model Checking

Partial order techniques enable reducing the size of the state space used for model checking, thus alleviating the “state space explosion” problem. These reductions are based on selecting a subset of the enabled operations from each program state. So far, these methods have been studied, implemented, and demonstrated for assertional languages that model the executions of a program as computation sequences, in particular the linear temporal logic. The present paper shows, for the first time, how this approach can be applied to languages that model the behavior of a program as a tree. We study here partial order reductions for branching temporal logics, e.g., the logics CTL and CTL* (with the next time operator removed) and process algebra logics such as Hennesy–Milner logic (withτactions). Conditions on the selection of subset of successors from each state during the state-space construction, which guarantee reduction that preserves CTL* properties, are given. The experimental results provided show that the reduction is substantial.     

Evaluating real-time software specification languages

In recent years, many notations and methods in real-time software engineering have been proposed. However, thorough experimentation to evaluate these notations and methods has not been carried out. This paper focuses on real-time software engineering specification languages: Unified Modeling Language (UML), Real-Time Object-Oriented Modeling Language (ROOM), Modecharts, statecharts, Mealy and Moore machines, finite state machines, classical logic, Z, ASTRAL, temporal logic, FNLOG, linear logic, Timed Communicating Sequential Processes (TCSP), Temporal Calculus of Communicating Systems (TCCS), ρ1, and Multilevel Specification. The basis for evaluating these software engineering specification languages is by using the Turing machines and Interaction machines. We classify them based on their computational capabilities.     

Design of a PID-like compound fuzzy logic controller

The paper describes a novel method for the design of a fuzzy logic controller (FLC) with near-optimal performance for a variety of operating conditions. The approach is based on the analysis of the system behaviour in the error state-space. The final control structure, in a form of a compound FLC, is arrived at in two stages. The first stage encompasses design and tuning of a PID-like fuzzy controller. The second stage consists of placing an additional fuzzy controller, of a structure similar to that of the first one, in parallel with the PID-like fuzzy controller designed in the first stage. The resulting compound controller is characterised with high performance in the wide range of operating conditions, and with small number of parameters that can be adjusted using simple optimisation methods. The controller is developed and tested for a plant comprising a vector controlled induction motor drive.     

AVSP算法

AVSP(Automatic Verifier of Secrurity Protocols)是基于串空间模型(Strand Space Model),并结合使用定理证明和模型检测技术开发出来的密码安全协议自动验证工具。AVSP使用了理想的语义和逻辑来表达安全协议的保密性,同时采用了一些证明策略以控制和减少状态空间爆炸的规模,并加快发现协议中存在的漏洞。     

Anxiety-based affective communication for implicit human-machine interaction

An implicit human-machine interaction framework that is sensitive to human anxiety is presented. The overall goal is to achieve detection and recognition of anxiety based on physiological signals. This involves building an anxiety-recognition system capable of interpreting the information contained in physiological processes to predict the probable anxiety state. Since anxiety plays an important role in various human-machine interaction tasks and can be related to task performance, the presented anxiety-recognition methods can be potentially applied to the design of advanced machines and engineering systems capable of intelligent decision-making while interacting with humans. Regression tree and fuzzy logic methodologies have been investigated for the above task. This paper presents the results of applying these two methods and discusses their comparative merits. Three human participant experiments were designed and trials were conducted with five participants. The experimental results demonstrate the feasibility of the proposed anxiety-recognition methods. To the best of our knowledge, our work is the first consolidated effort at fusing multiple physiological indices for robust, real-time detection of anxiety using pattern recognition methods such as fuzzy logic and regression trees.     

Adaptive fuzzy dynamic surface control for a class of stochastic MIMO discrete-time nonlinear pure-feedback systems with full state constraints

This paper presents the design of an adaptive fuzzy dynamic surface control for a class of stochastic MIMO discrete-time nonlinear pure-feedback systems with full state constraints using a set of noisy measurements. The design approach is described as follows. The nonlinear uncertainty is approximated by using the fuzzy logic system at the first stage, secondly the proposed adaptive fuzzy dynamic surface control is designed based on a new saturation function for full state constraints, thirdly the number of the adjustable parameters is reduced by using the simplified extended single input rule modules, and finally the simplified weighted least squares estimator is in a simplified structure designed to take the estimates for the un-measurable states and the adjustable parameters. The simulation provides that the proposed approach is effective for the improvement of the system performance.     

连续搅拌反应釜的固定时间命令滤波跟踪控制

针对一类连续搅拌反应釜系统的跟踪控制问题,提出一种基于反步法和模糊逻辑系统的自适应固定时间命令滤波控制方法.利用命令滤波器引入误差补偿机制消除滤波误差的影响,并解决反步法虚拟控制信号重复求导的问题;采用模糊逻辑系统对系统中存在的非线性部分进行逼近;利用固定时间控制方法使系统跟踪误差更迅速收敛至较小邻域内,且收敛时间不依赖系统初始状态;通过Lyapunov定理证明连续搅拌反应釜系统的闭环稳定性;利用Matlab/Simulink仿真实验验证所提出控制方法的有效性.与现有控制方法相比,该控制方法具有控制器结构简单、收敛速度快、控制精度高、无超调等优点.     

小规模频繁子电路的规律性预提取算法

针对数字IC规律性提取算法复杂度过高的问题,提出一种逐级对根节点进行分类的算法.通过对频繁边的直接扩展,实现了小规模频繁子电路的快速提取;利用门级电路中小规模频繁子电路与大规模频繁子电路间的结构依赖性,解决了候选子电路生成时根节点组合爆炸的问题.实验结果表明,该算法能够降低根节点的数量,使支持度高的候选子电路得到优先提取,并显著地减少了规律性提取的时间.     

Interval logics and their decision procedures : Part II: a real-time interval logic

In a companion paper, we presented an interval logic, and showed that it is elementarily decidable. In this paper we extend the logic to allow reasoning about real-time properties of concurrent systems; we call this logic real-time future interval logic (RTFIL). We model time by the real numbers, and allow our syntax to state the bounds on the duration of an interval. RTFIL possesses the “real-time interpolation property,” which appears to be the natural quantitative counterpart of invariance under finite stuttering. As the main result of this paper, we show that RTFIL is decidable; the decision algorithm is slightly more expensive than for the untimed logic. Our decidability proof is based on the reduction of the satisfiability problem for the logic to the emptiness problem for timed Büchi automata. The latter problem was shown decidable by Alur and Dill in a landmark paper, in which this real-time extension of ω-automata was introduced. Finally, we consider an extension of the logic that allows intervals to be constructed by means of “real-time offsets”, and show that even this simple extension renders the logic highly undecidable.     

基于时序逻辑的3种网络攻击建模

与其他检测方法相比,基于时序逻辑的入侵检测方法可以有效地检测许多复杂的网络攻击。然而,由于缺少网络攻击的时序逻辑公式, 该方法不能检测 出常见的back,ProcessTable以及Saint 3种攻击。因此,使用命题区间时序逻辑(ITL)和实时攻击签名逻辑(RASL)分别对这3种攻击建立时序逻辑公式。首先,分析这3种攻击的攻击原理;然后,将攻击的关键步骤分解为原子动作,并定义了原子命题;最后,根据原子命题之间的逻辑关系分别建立针对这3种攻击的时序逻辑公式。根据模型检测原理,所建立的时序逻辑公式可以作为模型检测器(即入侵检测器)的一个输入,用自动机为日志库建模,并将其作为模型检测器的另一个输入,模型检测的结果即为入侵检测的结果,从而给出了针对这3种攻击的入侵检测方法。