Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology

BiCMOS technologies have been used to implement the radio-frequency (RF) integrated circuits (ICs) due to the advantages of low noise, low power consumption, high drive, and high speed. The electrostatic discharge (ESD) is one of the important reliability issues of IC. When the ESD events happen, the ESD protection devices must be turned on immediately to protect the ICs, including the RF ICs in BiCMOS technologies. In this work, the vertical NPN (VNPN) devices in 0.18 μm silicon-germanium (SiGe) BiCMOS technology with base-emitter shorted and resistor trigger approaches are investigated. In component-level, using transmission-line-pulsing (TLP) and ESD simulator test the IV characteristics and human-body-model (HBM) robustness of the VNPN devices, respectively. In system-level, using ESD gun tests the system-level ESD robustness. The ESD protection of VNPN devices are further applied to a 2.4 GHz low-noise amplifier (LNA). After attaching the VNPN devices to LNA, the RF characteristics are not degraded while the ESD robustness can be much improved.     

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [forGPS receiver]

In recent years, much research has been carried out on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies, for radio-frequency (RF) applications. An example of such an application is the Global Positioning System (GPS). One of the important bottlenecks to make the transition to pure CMOS is the immunity of the circuits against electrostatic discharge (ESD). This paper shows that it is possible to design a low-noise amplifier (LNA) with very good RF performance and sufficient ESD immunity by carefully co-designing both the LNA and ESD protection. This is demonstrated with a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human body model (HBM) with a power consumption of 9 mW. The circuit was designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is implemented in a standard 0.25-μm 4M1P CMOS process     

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme was modified from the conventional double-diode ESD protection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

A review on RF ESD protection design

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.     

Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.     

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ${sim}2$ nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient $S_{11}$ is below ${-}13.0$ dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ${sim}40$ fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ${sim}100$ V/fF) among the published results for RF LNA applications.      

Interconnect Macromodelling and Approximation of Matrix Exponent

Electrostatic discharge (ESD) protection circuit design for radio-frequency (RF) integrated circuits emerges as a new design challenge. Yet currently, RF ESD protection is still a problem in definition. This paper proposes a new and comprehensive ESD-circuit interaction theory to address the complex mutual influences between the ESD protection networks and the circuits being protected in both directions. Design examples demonstrating the relevant key factors, e.g., switching and accidental triggering of ESD protection networks, as well as ESD-induced parasitic capacitive, resistive, noise coupling and self-generated noise effects, are provided to justify the new theory. Evaluation techniques, including s-parameter, Q-factor and overall specification examination, are discussed. The solutions to RF ESD protection are low-parasitic compact protection structures.     

Comprehensive ESD protection for RF inputs

We demonstrate that narrow-band tuned circuits may be used for ESD protection of RF inputs, and a figure of merit for optimization of these circuits is presented. The performance of the ESD-protected RF circuit is dependent on the quality factor of the ESD device, and various protection devices are evaluated in this work. Record-breaking human body model (HBM) protection levels, exceeding 5 kV, have been achieved without significantly degrading the RF performance at 5 GHz. Broadband circuit protection is also addressed.     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

A plug-and-play wideband RF circuit ESD protection methodology: T-diodes

A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18 μm CMOS is protected above 4.5 kV HBM ESD robustness without degrading its bandwidth.     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection

An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-$mu{hbox{m}}$ CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection ( $≪$350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.      

SCR器件在CMOS静电保护电路中的应用

静电放电(ESD)对CMOS电路的可靠性构成了很大威胁。随着CMOS电路集成度的不断提高，其对ESD保护的要求也更加严格。针对近年来SCR器件更加广泛地被采用到CMOS静电保护电路中的情况，文章总结了SCR保护电路发展过程中各种电路的工作机理。旨在为集成电路设计人员提供ESD保护方面的设计思路以及努力方向。     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

r of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level.Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.