An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10^-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.     

Ultrafast time-division demultiplexer based on electrooptic on/offgates

Electrooptic on/off gate-based demultiplexers for high-bit-rate optical transmission systems are reported. The electrooptic demultiplexing of a TDM 49.6 Gb/s fixed pattern data stream is demonstrated, using two cascaded Ti:LiNbO₃ electroabsorptive multi-quantum-well intensity modulators driven at 6.2 GHz. Error-free 10 Gb/s demultiplexing to 5 Gb/s is achieved using cascaded Mach-Zehnder (MZ) modulators driven at 1.25 GHz. The power penalty due to the interchannel crosstalk is 0.3 dB at the bit error rate of 10^-9     

Parallel-optical interconnects >100 gb/s

A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s giving an aggregate data rate of 102 Gb/s is demonstrated, to the authors' knowledge, for the first time. The paper describes and demonstrates 13 /spl times/ 16-mm cross-section 12-channel parallel-optic transmitter and receiver modules with each channel operating at a data rate of 8.5-10 Gb/s. This was achieved using bottom-emitting 990-nm vertical-cavity surface-emitting lasers and bottom-illuminated InGaAs-InP photodetectors flip-chip bonded directly to 12-channel transmitter and receiver integrated circuits, respectively. In addition, 102-Gb/s link results are demonstrated over 100 m of 50-/spl mu/m-core standard multimode ribbon fiber. A bit-error ratio of <10/sup -13/ was measured on a single channel after transmission through 100 m of multimode fiber at a data rate of 8.5 Gb/s with all 12 channels operating simultaneously.     

GaAs VCSEL's at λ=780 and 835 nm for short-distance 2.5-Gb/splastic optical fiber data links

Selectively oxidized GaAs vertical-cavity surface-emitting lasers for λ=780- and 835-nm emission wavelength and 120-μm-core diameter step index plastic optical fiber (POF) are investigated for short distance interconnects. 2.5-Gb/s pseudorandom data transmission over up to 2.5 m of plastic fiber is demonstrated with a bit-error rate (BER) of better than 10^-11. Furthermore, bias-free data transmission at 2.5 Gb/s over 1-m fiber length again at a BER of better than 10^-11 is reported     

3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly

This paper presents a 3D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 mum CMOS implementation demonstrate working connections with an area occupation of 8 times 8 mum² . Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/muM² with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than transmitted.     

A Power-Efficient Clock and Data Recovery Circuit in 0.18 μm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 mum CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm² /channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is plusmn3.5% and no error was detected for a 2³¹-1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10^-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.      

Densely spaced FDM coherent star network with optical signalsconfined to equally spaced frequencies

The results obtained with a fiber-optical star network using densely spaced frequency-division-multiplexing (FDM) and heterodyne detection techniques are discussed. The system consists of three optical sources transmitting around 1.28 μm, frequency-shift keying (FSK) modulated at 45 Mb/s and spaced by 300 MHz. A 4×4 optical coupler combines the three optical signals. The FDM signals, received from one of the four outputs of the coupler, are demultiplexed by a heterodyne FM receiver. The minimum received optical power needed to obtain a bit error rate (BER) of 10^-9 is -61 dBm or 113 photons/bit, which is 4.5 dB from the shot noise limit. Cochannel interference is negligible for the above channel spacing and modulation rate. The results indicate that such a system has a potential throughput of 4500 Gb/s. The results obtained with two frequency stabilization circuits used to confine these three FDM optical signals to a comb of equally spaced frequencies are also presented     

A 12.5 Gb/s Si bipolar IC for PRBS generation and bit errordetection up to 25 Gb/s

This paper describes a Si bipolar IC which features PRBS generation, bit error detection, (de-) scrambling, and trigger derivation up to 12.5 Gb/s. The sequence length is switchable between 2 ¹¹-1 and 2¹⁵-1 b. Two input/output channels are provided which allow PRBS testing up to 25 Gb/s with one external MUX/DMUX. The 3×4 mm², 1377 transistor chip uses 0.4 μm emitter 25-GHz-f_T single-poly self-aligned Si bipolar technology and dissipates 4.6 W from a single -5 V supply     

Proton implanted VCSEL's for 3 Gb/s data links

Transverse single-mode and multimode intensity modulated butt-coupled InGaAs vertical cavity surface emitting lasers (VCSEL)s are investigated as a light source for optical fiber communication systems. Data transmission at 3 Gb/s with a bit error rate (BER) of less than 10 ^-11 is reported for both 4.3 km of standard fiber, as well as 0.5 km of multimode graded-index fiber, 10-μm active diameter single-mode VCSELs are shown to have lower mode competition noise requiring 3 dB and 6 dB less power at the front end receiver at a BER of 10^-11 compared to 19-μm and 50-μm active diameter devices, respectively. In data transmission with multimode VCSELs, the dispersion penalty is lower than for single-mode sources since the noise at the receiver is mainly determined by transmitter-mode competition noise     

Ge-on-SOI-Detector/Si-CMOS-Amplifier Receivers for High-Performance Optical-Communication Applications

In this paper, an overview and assessment of high-performance receivers based upon Ge-on-silicon-on-insulator (Ge-on-SOI) photodiodes and Si CMOS amplifier ICs is provided. Receivers utilizing Ge-on-SOI lateral p-i-n photodiodes paired with high-gain CMOS amplifiers are shown to operate at 15 Gb/s with a sensitivity of -7.4 dBm (BER=10^-12) while utilizing a single supply voltage of only 2.4 V. The 5-Gb/s sensitivity of similar receivers is constant up to 93 degC, and 10-Gb/s operation is demonstrated at 85 degC. Error-free (BER<10^-12) operation of receivers combining a Ge-on-SOI photodiode with a single-ended high-speed receiver front end is demonstrated at 19 Gb/s, using a supply voltage of 1.8 V. In addition, receivers utilizing Ge-on-SOI photodiodes integrated with a low-power CMOS IC are shown to operate at 10 Gb/s using a single 1.1-V supply while consuming only 11 mW of power. A perspective on the future technological capabilities and applications of Ge-detector/Si-CMOS receivers is also provided     

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV_pp with for input spanning from to . The measured integrated input-referred noise is 3.3muA_rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2³¹ - 1 PRBS input, the recovered clock jitter is and 0.7ps_rms. The retimed data exhibits 13.3 ps_pp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.     

27-GHz bandwidth high-speed monolithic integrated optoelectronicphotoreceiver consisting of a waveguide fed photodiode and anInAlAs/InGaAs-HFET traveling wave amplifier

A monolithic integrated photoreceiver for 1.55-μm wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-μm gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dBΩ. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10^-9) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10^-9) [including erbium doped fiber amplifiers (EDFA)]     

High-speed QPSK modulator and demodulator with subharmonic pumping

The authors describe a subharmonically pumped QPSK modulator and demodulator using pairs of beam-leaded Schottky diodes and appropriate high-pass and low-pass filters on dielectric substrates. A modulator and a demodulator were operated in cascade at a carrier frequency of 13 GHz with a common pump at 6.5 GHz. This circuit showed clean eye diagrams of the recovered data trains up to 1.5 Gb/s with corresponding error rates of less than 10^-11. The circuits can be readily scaled to higher frequencies with a proportional increase of the information rate     

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11- μm CMOS

This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid separates the inbound signal from the signal line voltage and current without using a replica driver. It eliminates the need for precise matching between the replica- and main-driver characteristics, enabling a data rate of 20 Gb/s per differential pair, which is the highest reported for bidirectional signaling. The transceiver occupies 1.0² mm and consumes 260 mW at 20 Gb/s with a bit error rate of less than 10^-12. The area and power overhead due to the hybrid are 0.002 mm² and 7 mW, and correspond to 0.2% and 3% of the total transceiver area and power consumption     

Optical input buffers for the HiPower photonic ATM switch-analysisand experiments

We describe an optical input buffer for the HiPower photonic ATM switch. This buffer can control the cell throughput in accordance with back pressure signals and incoming optical cells. We analyze the cell loss probability of the optical input buffer. Only a small buffer size of five is needed to obtain a cell loss probability of less than 10^-15 with 1024 ports. Experimental 10 Gb/s operation using optical fiber delay lines with gate control circuits shows that the bit error rate of the buffer is less than 10^-12     

A 10-Gb/s silicon bipolar IC for PRBS testing

A 10 Gb/s silicon bipolar IC for pseudorandom binary sequence (PRBS) testing was fabricated and tested. The IC features PRBS generation of the sequences of length 2¹⁵-1 and 2²³-1 b up to 10 Gb/s according to CCITT recommendations. Furthermore, the IC is capable of analyzing PRB sequences of the same length and generation polynomials so that a full test of components is possible. In addition, a new PRBS test word synchronization can be provided between two chips for external multiplexing of the sequences up to 40 Gb/s. The IC can be connected to a standard PC, so evaluation of the error test data can be performed in a flexible way. The IC was fabricated with the HP25 process of Hewlett Packard company, the chip size is 32 mm², and it consumes 6.2 W at the nominal supply voltage of -5 V     

A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS

An 8-PAM CMOS transceiver is described in this paper. Pre-emphasis is implemented without an increase in DAC resolution or digital computation. The receiver oversamples with three fully differential 3-bit ADCs. The prototype transmits at up to 1.3 Gb/s and has a measured bit error rate of less than 1 in 10¹³ for an 810-Mb/s pseudorandom bit sequence transmission. The device, packaged in a 68-pin ceramic leadless chip carrier, is implemented in 0.5-μm digital CMOS, occupies 2 mm², and dissipates 400 mW from a 3.3-V supply