1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique     

1-V bulk-driven CMOS analog programmable winner-takes-all circuit

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail. This work was in part supported by the Chip Implementation Center and the MOE Program of Promoting Academic Excellence of Universities under the Grant EX-93-E-FA09-5-4. Yu-Cherng Hung was born in Changhua, Taiwan, R.O.C., in 1964. He received the M. S. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 1992, and the Ph.D. degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2004. From Dec. 1986 to Jan. 2005, he was with the Division of Computer/Information, Chinese Petroleum Corp., Taiwan. He is currently an Assistant Professor with the Department of Electronic Engineering, National Chin-Yi Institute of Technology, Taiwan, R.O.C. His main research interests include analog circuit design, low-voltage VLSI design, and neural network applications. Dr. Hung is a Member of Phi Tau Phi Honorary Scholastic Society, IEEE, and the Institute of Electronics, Information, and Communications Engineers (IEICE). Bin-Da Liu received the Ph.D. degrees in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1983. Since 1977, he has been on the faculty of the National Cheng Kung University, where he is currently a Distinguished Professor in the Department of Electrical Engineering and the Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995, he has been a Consultant of the Chip Implementation Center, National Applied Research Laboratories, Hsinchu, Taiwan. He has published more than 200 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). His current research interests include low power circuit, neural network circuit, CMAC neural network, analog neural network architecture, design of programmable cellular neural networks, and very large-scale integration implementation of fuzzy/neural circuits and audio/video signal processors. Dr. Liu is a Fellow of IEEE and the Vice President of Region 10, IEEE Circuits and Systems Society. He served as a CAS Associate Editor of IEEE Circuits and Devices Magazine and an Associate Editor of IEEE Transactions on Circuits and Systems I: Regular Papers. He is serving as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Chung-Yang Tsai was born in Mian-Li, Taiwan, R.O.C. He received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 2001 and 2003, respectively. His research interests include very large-scale integration design and signal processing.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

A CMOS bandgap reference circuit with sub-1-V operation

This paper proposes a CMOS bandgap reference (BGR) circuit, which can successfully operate with sub-1-V supply, In the conventional BGR circuit, the output voltage V_ref is the sum of the built-in voltage of the diode V_f and the thermal voltage V_T of kT/q multiplied by a constant. Therefore, V_ref is about 1.25 V, which limits a low supply-voltage operation below 1 V. Conversely, in the proposed BGR circuit, V_ref has been converted from the sum of two currents; one is proportional to V_f and the other is proportional to V_T. An experimental BGR circuit, which is simply composed of a CMOS op-amp, diodes, and resistors, has been fabricated in a conventional 0.4-μm flash memory process. Measured V_ref is 518±15 mV (3σ) for 23 samples on the same wafer at 27-125°C     

A 1-V high-speed MTCMOS circuit scheme for power-down applicationcircuits

This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSI's) for battery-driven portable equipment. The “balloon” circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-μm CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices     

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-μm CMOS process. Experimental results are provided and the corresponding performances are discussed and compared     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

Design of sub-1-V CMOS bandgap reference circuit using only one BJT

This paper describes new CMOS bandgap reference (BGR) circuits capable of providing sub-1-V voltage reference while using only one BJT. The circuits use the concept of reverse bandgap voltage principle (RBVP) to generate attenuated versions of the silicon bandgap voltage of 1.205?V. Also, as opposed to the previously known sub-1-V BGR by Banba et?al. (IEEE J Solid State Circuits 34:670?C674, 1999), the circuits can be operated with lower supply voltage down to a 1.3?V supply. Based on the scheme, a 550?mV BGR is implemented in 65?nm CMOS process, with peak-to-peak variation of 7.19?mV across devices corners, temperature range of ?20 to 80° and supply range of 1.6?C2.0?V.     

智能数字供电技术浅析

本文通过介绍现有数字技术已经发展到一个较高高度,但能源领域的数字化控制及软件定义程度相对较低。为实现能源领域的高效供电与储能,将数字化技术全面而又恰当的引入能源领域是今后实现数字能源、软件定义能源的必然趋势。本文分析了现有通信电源领域中典型技术,列举并分析了几种可以应用于数字能源领域的电源技术方案,引出数字能源发展需要面对的技术要点与问题,为今后数字能源发展做好技术储备。     

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.     

标准CMOS工艺在高速模拟电路和数模混合电路中的应用展望

从速度、集成度、功耗和成本等几个方面深入的分析了利用标准CMOS工艺来设计开发高速模拟器件和混合处理芯片的现状及发展潜力。     

Sub-1-V CMOS proportional-to-absolute temperature references

Presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (/spl mu/A) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-/spl mu/W integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-/spl mu/m very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+>60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies.     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

基于EDA技术的航空电源逆变控制电路设计

为适应航空电源品质的新需求和发展的快节奏,综合先进的现代EDA技术与脉宽调制技术,精心设计航空逆变电路的调制方案。采纳等效面积正弦波脉宽调制(SPWM)生成法构建控制数学模型,通过数值运算和数字转换,运用硬件描述语言VHDL编写实现设计所需的逻辑功能。以PLD元器件为调制控制电路的硬件,采用Max+PlusⅡ软件在EDA实验开发系统(GW-GK系统)上完成仿真和硬件测试实验,获得了三相SPWM波形脉冲序列,实现了数字化控制,确保了输出波形谐波量小,波形接近理想正弦波形,同时简化了控制电路的结构和规模,提高系统的控制精度及其可靠性。     

基于PMBus和VID技术的电源电路设计

针对高速嵌入式系统对自动调节输出电压的电源系统的需求,本文采用PMBus总线为电源芯片之间,电源芯片和控制器之间的通信提供标准,通过重点分析基于PMBus总线的数字可编程电源的内部结构和电压识别的技术实现方法,设计了一支持电压识别(VID)技术的带两路独立电压输出的数字可编程电源系统。经PMBus总线进行配置后,该电源系统可以满足高速嵌入式系统的多种电压需求,取得了良好的效果。     

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50 ps width with ~17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Giga-sample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.     

BiCMOS circuit technology for high-speed DRAMs

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed     

高速数字电路电源系统的电磁兼容研究

随着实时信号处理的速率不断加快,数字电路系统的时钟频率也随之增加。同时,半导体工艺的改进,也使得电路系统中信号边沿速率提升到ns级甚至更高的级别。快速的信号边沿变化使得电路信号产生振铃、反射、串扰、地弹等许多信号完整性问题。而且,这个问题越来越严重。随着电路中器件和芯片工作环境的恶化,电源受到的影响非常严重,电源系统的电磁兼容性设计变得更加富有挑战性。研究电源系统的电磁兼容性设计非常有必要而且非常紧迫。     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed