FLOTOX—E^2PROM阈值电压的研究

本文讨论了理想情况下ＦＬＯＴＯＸ结构Ｅ＾２ＰＲＯＭ在斜坡脉冲作用下的阈值电压变化，并对隧道氧化层中存在净电荷时的情况作了讨论。模拟结果表明适当的斜坡脉冲电压可处ＦＬＯＴＯＸ结构Ｅ＾２ＰＲＯＭ的寿命。     

一种适合于ASIC应用的新的工艺技术—CMOS逻辑VLSIE^2PROM的单片集成

我们开发了一种新的工艺技术，实现了在ＣＭＯＳ ＶＬＳＩ制造中嵌入Ｅ＾２ＰＲＯＭ的制造技术。在此新工艺中，制造的是单层多晶硅的Ｅ＾２ＰＲＯＭ。与传统的双层多晶硅Ｅ＾２ＰＲＯＭ的工艺相比，减少了２５％的工序。通过采用三种不同厚度的栅氧化层，可以缩小在ＣＭＯＳＶＬＳＩ中嵌入的Ｅ＾２ＰＲＯＭ的器件尺寸。器件工作电压范围宽为１．５－６Ｖ，静态电流低于１００ｎＡ。     

RTP改善超薄SiO2膜特性的研究

超薄ＳｉＯ２膜经快速热处理后，电特性得到了改善，本研究用超薄ＲＴＰＳｉＯ２膜制作ＭＯＳ电容，ｈ－ＮＭＯＳＦＥＴ中介栅介质层及ＦＬＯＴＯＸ－Ｅ＾２ＰＲＯＭ中作隧道氧化层，取得了一些实验结果，从结果中可以看出具有实有价值。     

MOCVD生长带有MQB的量子阱激光器材料

用ＭＯＣＶＤ生长发射波长为８０８ｎｍ的ＡｌＧａＡｓ／ＧａＡｓ量子阱激光器材料。通过在激光器材料的波导中加入多量子势垒（ＭＱＢ）层，有效地限制电子在阱内的复合以及高能电子溢出阱外，从而降低了激光器的阈值电流，提高了它的特征温度。增加了ＭＱＢ后，器件的阈值电流密度Ｉｔｈ从原来的４００￣６００Ａ／ｃｍ＾２下降到３００￣４００Ａ／ｃｍ＾２，特征温度从１６０Ｋ提高到２１０Ｋ。     

FLOTOX EEPROM存储管的简单模型分析和实验研究

分析了ＦＬＯＴＯＸ ＥＥＰＲＯＭ的简单电路模型和擦写特性。实验研究了不同的器件结构参数和擦写脉冲对存储管特性的影响，表明隧道氧化层和多晶之间介质层的厚度对ＥＥＰＲＯＭ阈会晤窗口有很大的影响、采用指数上升波形或三角波形进行了编程可以改善ＥＥＰＲＯＭ的耐久性。     

多功能电子皮带秤控制仪

本文介绍了一种基于单片机综合技术的新型多功能电子皮带秤控制仪。该控制仪系统设计新颖，配有毫伏放大电路、Ａ／Ｄ、Ｄ／Ａ、ＤＩ、ＤＯ，采用Ｅ＾２ＰＲＯＭ实现系统、控制参数和累积数据的断电保护，可完成单／多台电子皮带秤的自动称量显示、标定、定量和配比ＰＩ控制以及通信、打印等功能。     

超薄SiO2层的热生长

隧道小孔中超薄ＳｉＯ２的生长是ＥＥＰＲＯＭ电路制造的关键工艺之一。采用ＳＵＰＲＥＭ－Ⅲ工艺模拟程序对超薄ＳｉＯ２的热生长进行了工艺模拟，经过大量的工艺实验及优化，确定了超薄ＳｉＯ２的最佳生长条件，生长出的ＳｉＯ２性能良好，完全可满足ＥＥＰＲＯＭ研制的要求。     

一种全功能2kb E^2PROM的研制

论述了Ｅ＾２ＰＲＯＭ的设计技术，包括单元设计，升压电路设计，存储阵列设计等，然后扼要介绍了其工艺过程和关键工艺，最后给出了Ｅ＾２ＰＲＯＭ单元和电路的性能。     

串行E^2PROM AT24CXX的原理及应用

本文分析了美国爱特梅尔（ＡＴＭＥＬ）公司生产的最新二线式串行ＣＭＯＳＥ＾２ＰＲＯＭ芯片ＡＴ２４Ｃ０１／０２／０４／０８／１６的内部结构性能特点，读写时序，并说明了使用方法。     

膜厚和消光距离的CBED测定中实验结果的拟合

根据薄晶（片）膜厚和消光距离的ＣＢＥＤ测定原理，经过适当数学处理，编制计算ｓ＾２／ｘ＾２与１／＾２值、并有利于对实验结果进行拟合的计算程序ＣＢＥＤ。应用此程序测定了γ薄晶和ＭＣ片的厚度和消光距离。所进行的拟合基于：对含有两个满足Ｂｒａｇｇ条件的衍射的ＣＢＥＤ图，ｓ＾２／ｘ＾２与１／ｘ＾２关系直线有相同的截距；对某一衍射的两张以上的ＣＢＥＤ图，这些直线有相同斜率。     

E~2PROM擦/写特性的PCM研究

使用薄隧道氧化层浮栅器件逐渐成为在电可擦除稳定的存储器中一个标准[1]，根据E~2PROM工艺特点，本文着重分析了E／W后学元开启电压和E／W时间。E／W电压、隧道扎面积的关系。给出了开发和研究E~2ROM器件模型的工艺评价用PCM及常规用PCM的测试结果，为E~2PROM的工艺开发和实现提供有力的帮助。根据浮栅E~2PROM的物理模型[2]，建立了存储单元的阈值电压模型，利用该模型研究了存储单元E／W后同值电压与物理尺寸、E／W电压、E／W时间的关系。通过对这一关系更深入的认识，一方面在单元设计上有利于了解不同类型的E~2PROM，为减小器件尺寸以及今后开发业微米的设计规则作准备；另一方面，在工艺上建立一个准确的单元添件参数模型，得到各层次各关键工序的工艺评价参数，为制造高性能高可靠性的存储单元打下坚实基础。     

Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides

This paper reports on the effect of fluorine incorporation on gate-oxide reliability, especially the spatial distribution of charge-to-breakdown (Q/sub BD/). Fluorine atoms were implanted into gate electrodes and introduced into gate-oxide films by annealing. Excess fluorine incorporation increased the oxide thickness and degraded not only the reliability of Si/SiO/sub 2/ interfaces but also dielectric-breakdown immunity. However, it was found, for the first time, that appropriate fluorine incorporation into gate-oxide films could dramatically improve Q/sub BD/-distribution tails in Weibull plots, while maintaining both Si/SiO/sub 2/ interface characteristics and average Q/sub BD/ values. The experimental result for a depth profile of fluorine atoms indicated that fluorine atoms are located dominantly at the two interfaces of the gate-oxide film. In addition, the results of infrared (IR) absorption analysis indicated that the strain of SiO/sub 2/ structures is reduced with increasing fluorine doses. We proposed that both strain release and restructuring of the SiO/sub 2/ network by fluorine incorporation are responsible for improving the Q/sub BD/ of weaker oxide films.     

A 16K E/SUP 2/PROM using E/SUP 2/ element redundancy

A new LSI memory redundancy technique using E/SUP 2/PROM cells as the programmable element has been developed. Yield enhancement with this technique has been demonstrated using two redundant rows on a 16K E/SUP 2/PROM chip. This paper describes the structure and operation of the circuit blocks used, and how these circuits interface with the memory chip to produce the observed yield enhancement. The method for programming the redundancy elements is described, along with circuit advantages and capabilities unique to E/SUP 2/PROM redundancy. Device performance and yield enhancement for the 16K E/SUP 2/PROM are summarized.     

New insights in polarity-dependent oxide breakdown for ultrathin gate oxide

In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown.     

薄栅氧化层击穿特性的实验研究

在恒流应力条件下测试了薄栅氧化层的击穿特性,研究了ＴＤＤＢ的击穿机理,讨论了栅氧化层面积对击穿特性的影响．对相关击穿电荷ＱＢＤ进行了实验测试和分析,研究结果表明：相关击穿电荷ＱＢＤ除了与氧化层质量有关外,还与应力电流密度以及栅氧化层面积强相关．得出了ＱＢＤ的解析表达式,并且对相关参数进行了研究     

Successful enhancement of lifetime for SiO/sub 2/ on 4H-SiC by N/sub 2/O anneal

Time-dependent dielectric breakdown (TDDB) measurement by constant current stress has been performed to investigate the oxide (SiO/sub 2/) reliability grown on n-type 4H-SiC. At 300K, the intrinsic injected charge to breakdown (Q/sub BD/) of thermally grown SiO/sub 2/ in wet O/sub 2/ ambience is about 0.1 C/cm/sup 2/, whereas N/sub 2/O anneal after the thermal oxidation results in the drastic improvement of the reliability. The intrinsic Q/sub BD/ of N/sub 2/O annealed SiO/sub 2/ is found to be 10 C/cm/sup 2/, which is two orders of magnitude larger than that of the oxide without N/sub 2/O anneal, suggesting that the quality of SiO/sub 2/ and/or SiO/sub 2//SiC interface is improved. TDDB measurement has been also performed at high temperatures up to 423 K. The activation energy of oxide lifetime estimated from time to failure of 80% is 0.35 and 0.10 eV for the oxide with and without N/sub 2/O anneal, respectively.     

Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH/sub 3/ and N/sub 2/O nitridation

This brief presents a new nitridation process on a floating poly-Si gate to improve the quality of both tunneling oxide and interpoly-oxide of nonvolatile memories. Three types of poly-Si for a floating gate have been investigated. We found in-situ doped poly-Si shows the best performance in terms of breakdown field, charge-to-breakdown (Q/sub BD/) and trapping rate. The Q/sub BD/ of interpoly-oxide can be reached as high as 35 C/cm/sup 2/. This scheme is very promising for nonvolatile memory devices.     

A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology

A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8/spl times/8 /spl mu/m/SUP 2/, even with relatively conservative 2.0-/spl mu/m design rules, a small die size of 5.69/spl times/5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 /spl mu/s/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.     

薄栅介质TDDB效应

在恒压和恒流应力条件下测试了超薄栅氧化层的击穿特性 ,研究了 TDDB(Tim e Dependent DielectricBreakdown)的可靠性表征方法 .对相关击穿电荷量 QBD进行了实验测试和分析 .结果表明 :相关击穿电荷量 QBD除了与氧化层质量有关外 ,还与应力电压和应力电流密度以及栅氧化层面积有关 .对相关系数进行了拟合 ,给出了 QBD的解析表达式 .按照上述表达式外推的结果和实验值取得了很好的一致 .提出了薄栅介质 TDDB效应的表征新方法     

Control logic and cell design for a 4K NVRAM

A high-density 4K 5-V-only nonvolatile static RAM has been designed using a wafer stepper HMOS I FLOTOX E/SUP 2/PROM technology. Normal SRAM read/write operations and parallel data transfer between SRAM and E/SUP 2/PROM array are possible. On-chip high-voltage regulation and generation, junction leakage control, and self-timing circuitry ensure full military temperature operation. Power-down store lockout protection and power-up automatic recall are featured.