基于人工神经网的激光三维扫描技术研究

在激光三维测量技术中 ,用摄像机对物体和物体在平面反射镜中的虚像成像 ,用人工神经网技术实现图像坐标系到世界坐标系的映射 ,无须测定摄像机和激光平面之间的相对位置关系 ,自动修正镜头的几何畸变 ,由单视点序列影像就可获得被测物体表面的三维坐标。结论 :盲区小、方法简单 ,变换关系清晰 ,能获得高质量的测量结果。     

融合深度卷积网络与点云网络的三维车辆检测方法分析

在常规的车辆目标检测中,YOLO,SSD,RCNN等深度模型都获得了较好的检测效果,但是在无人驾驶系统中,车辆的速度、方向、相对距离等因素对于系统来说十分重要,所以采用二维车辆检测对于驾驶场景的理解还远远不够。激光点云数据蕴含着丰富的三维环境信息,融合点云数据和深度网络的三维车辆检测已成为未来的发展方向。文章给出了一种基于点云网络与卷积神经网络的三维车辆检测方法,首先,使用CRC和输入尺寸有关的SDP技术来提高车辆检测的准确性;其次,采用点云网络结构(Pointnet)来处理点云数据,实现三维目标检测,研究表明设计网络结构在检测精度上有着较大的优势。     

基于PID神经网络的无人机三维航迹控制方法研究

在研究无人机空中加油航迹控制时,发现二维航迹控制方法难以实现高精度的控制要求。其主要问题是二维航迹控制只能解算出水平面的位置,忽略了高度信息。主要描述了三维航迹控制方法及控制器设计。在二维导航控制的基础上,采用非定高航程推算原理解算出无人机实时位置信息。着重分析航点高度信息算法,飞控系统实时跟踪此计算高度,完成轨迹控制。控制器采用PID神经网络方法,与传统PID控制相比能明显改善控制器性能,响应快,超调小,稳态精度高,能够满足无人机三维航迹控制的飞行要求。     

基于3D卷积神经网络的PolSAR图像精细分类

PolSAR （Polarimetric Synthetic Aperture Radar）图像分类的传统方法在前期需要对数据进行特征提取,涉及较多的人为参与,且分类精度有待进一步提高。此外,在采用监督分类方法时,某些地物存在小样本问题,针对这些问题并结合PolSAR图像精细分类的需求,提出基于3D卷积神经网络的PolSAR图像地物精细分类方法,将传统卷积神经网络扩展为三维并将其应用于PolSAR图像分类中,利用PolSAR数据多通道特性,充分挖掘数据中的信息,提高分类性能,并采用虚拟样本扩充的方法改善某些地物的小样本情况,获得更好的分类结果。实验结果表明:3D卷积神经网络较2D卷积神经网络在PolSAR图像地物精细分类中有较好的性能,且虚拟样本扩充方法能够有效改善小样本分类问题。     

基于3D卷积神经网络的脑肿瘤医学图像分割优化

针对2D卷积神级网络不能够较好地提取各模态之间的差异信息,不同的图像层肿瘤大小差异显著,且分割精度低,单模态MRI无法清晰地反映GBM的不同组织结构,提出一种基于3D多池化卷积神经网络拟解决以上实际问题。将卷积神经网络应用到脑肿瘤分割上,并针对脑肿瘤的特点,提出3D多池化卷积神经网络模型,通过多尺度的输入与多尺度的下采样,且在后端使用条件随机场(CRF)使图片尽量在边界处分割,增加图像的分割精度,克服脑肿瘤的个体差异,同时适应脑肿瘤不同图像层之间的大小位置差异。通过对100例患者的多模态磁共振图像进行分割,Dice系数达到91.64%;MRI脑肿瘤分割的改进方法可使分割精度得到明显提高,可更好地提取各模态之间的差异信息,实现适应范围更广的MRI肿瘤分割,并准确有效地分割脑肿瘤。     

A reconfigurable VLSI neural network

Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently     

A neural network approach-decision neural network (DNN) for preference assessment

A new neural-network-based approach to assess the preference of a decision-maker (DM) for the multiple objective decision making (MODM) problem is presented in this paper. A new neural network structure with a "twin-topology" is introduced in this approach. We call this neural network a decision neural network (DNN). The characteristics of the DNN are discussed, and the training algorithm for DNN is presented as well. The DNN enables the decision-maker to make pairwise comparisons between different alternatives, and these comparison results are used as learning samples to train the DNN. The DNN is applicable for both accurate and inaccurate comparisons (results are given in approximate values or interval scales). The performance of the DNN is evaluated with several typical forms of utility functions. Results show that DNN is an effective and efficient way for modeling the preference of a decision-maker.     

Simulation of a novel, optically addressable,switched-current/continuous-time, current-mode cellular neural network

The authors describe simulation results of a novel GaAs-based current-mode cellular neural network (CNN) connected component detector. It uses a new two-stage integrator which may be operated in switched-current or continuous-time mode. Our system approach would afford CNN parallel optical input and output     

欧洲科学家设计出神经计算机原型

由欧盟支持的FACETS项目汇集了来自7个国家15个研究院所的科学家来从事神经计算机的研究.得益于神经科学研究的成果,正在构建一台像大脑一样工作的神经计算机,但规模要小得多.德国海德堡大学的物理学家卡尔海因茨·迈尔表示: "我们都知道大脑具有神奇的运算本领.我们即将开发的系统将借鉴大脑的生物学知识,也许将成为新一轮信息技术革命的一部分."     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

A 1.2 GFLOPS neural network chip for high-speed neural networkservers

This paper describes a digital neural network chip for high-speed neural network servers. The chip employs single-instruction multiple-data stream (SIMD) architecture consisting of 12 floating-point processing units, a control unit, and a nonlinear function unit. At a 50 MHz clock frequency, the chip achieves a peak speed performance of 1.2 GFLOPS using 24-bit floating-point representation. Two schemes of expanding the network size enable neural tasks requiring over 1 million synapses to be executed. The average speed performances of typical neural network models are also discussed     

Java3D在网络三维游戏设计中的应用探讨

随着网络技术、虚拟现实技术的迅猛发展、人们生活娱乐水平的提高,近几年三维网络游戏成为热门焦点.现介绍了三维网络游戏的发展现状,选择Java3D的优点并举例说明,也简要说明了它的一些不足之处.     

A neural network architecture for preattentive vision

Recent results towards development of a neural network architecture for general-purpose preattentive vision are summarized. The architecture contains two parallel subsystems, the boundary contour system (BCS) and the feature contour system (FCS), which interact together to generate a representation of form-and-color-and-depth. Emergent boundary segmentation within the BCS and featural filling-in within the FCS are emphasized within a monocular setting. Applications to the analysis of boundaries, textures, and smooth surfaces are described, as is a model for invariant brightness perception under variable illumination conditions. The theory shows how suitably defined parallel and hierarchical interactions overcome computational uncertainties that necessarily exist at early processing stages. Some of the psychophysical and neurophysiological data supporting the theory's predictions are mentioned     

A neuron-MOS neural network using self-learning-compatible synapsecircuits

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (υMOS) as a key circuit element. A υMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based on the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept υMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V_DD power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of υMOS neural networks. The basic operation of the synapse cell and a υMOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process     

神经网络通信故障检测

提出一种基于神经网络的通信设备故障检测手段,通过神经网络的宏观计算,化简故障分类策略,填补了现有故障检测手段的盲区,极大地提高了通信设备的可靠性.     

A vector neural network for emitter identification

This paper proposes a three-layer vector neural network (VNN) with a supervised learning algorithm suitable for signal classification in general, and for emitter identification (EID) in particular. The VNN can accept interval-value input data as well as scalar input data. The input features of the EID problems include the radio frequency, pulse width, and pulse repetition interval of a received emitter signal. Since the values of these features vary in interval ranges in accordance with a specific radar emitter, the VNN is proposed to process interval-value data in the EID problem. In the training phase, the interval values of the three features are presented to the input nodes of VNN. A new vector-type backpropagation learning algorithm is derived from an error function defined by the VNN's actual output and the desired output indicating the correct emitter type of the corresponding feature intervals. The algorithm can tune the weights of VNN optimally to approximate the nonlinear mapping between a given training set of feature intervals and the corresponding set of desired emitter types. After training, the VNN can be used to identify the sensed scalar-value features from a real-time received emitter signal. A number of simulations are presented to demonstrate the effectiveness and identification capability of VNN, including the two-EID problem and the multi-EID problem with/without additive noise. The simulated results show that the proposed algorithm cannot only accelerate the convergence speed, but it can help avoid getting stuck in bad local minima and achieve higher classification rate.     

Performance analysis of a large interconnected network bydecomposition techniques

A study that models the possible configurations of a proposed packet-transport-equipment (PTE)-based university campus network is reported. The function of these PTEs is to receive/forward data packets from/to remote LANs or workstations. The objective is to determine whether the traffic capacity of the proposed network can handle the projected university workload, how different applications impact network load, and where the potential system bottlenecks are. The modeling approach taken treats the interconnected LANs as a hierarchy with the fiber (backbone) ring as the apex. Both analytical and simulation models are developed, with simulation being preferred as the workloads approach saturation conditions     

A 3D multilayer optical network on chip based on mesh topology

Optical Network-on-Chip (ONoC) is becoming a promising solution for high performance on chip interconnection, which draws much attention from many researchers. ONoC combined with 3D integration technology can address some issues of two-dimensional ONoC such as long distance and limited scalability, which have been shown to be effective solutions for further promoting the performance of ONoC. However, the infeasibility of most existing routers with four or five ports poses a problem in 3D optical interconnect as seven-port optical routers are required in 3D networks. To solve this problem, in this paper, we propose a 3D multilayer optical network on chip (3D MONoC) based on Votex, a non-blocking optical router with seven ports. We describe the optical router and the 3D network in detail. The proposed router architecture not only realizes 3D interconnection and can be utilized in most 3D ONoC, but also can be beneficial in achieving smaller area, lower cost of ONoC. We compare Votex with the traditional \(7\times 7\) optical router based on crossbar, which indicated that Votex can save cost. Moreover, we make a comparison of 3D MONoC employing Votex against its 2D counterpart. Simulation results show that the performance including ETE delay and throughput of 3D MONoC can be improved.     

网络与信息安全测试原型系统的关键技术研究

主要研究了网络与信息安全原型系统中的关键技术，介绍了网络与信息安全测试平台的组成，阐述了测试方法。