Optical interconnects for neural and reconfigurable VLSIarchitectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits     

Optoelectronic implementations of neural networks

The ability of optical systems to provide the massive interconnections between processors required in most neural network models, which constitutes their chief advantage for such applications, is discussed, focusing on holography. Because of the essential nonlinearity of the holographic connections, nonlinear processing elements are needed to perform complex computations. The use of GaAs hybrid optoelectronic processing elements is examined. GaAs is an excellent material for this purpose, since it can be used to fabricate both fast electronic circuits and optical sources and detectors. It is shown how a complete hybrid neural computer can be implemented using available technology developed for conventional computing. An experimentally demonstrated network in which optics plays an even larger role is described     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

Parallel architectures for digital optical cellular imageprocessing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output     

Silicon on sapphire CMOS for optoelectronic microsystems

we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues     

Ultralow-threshold-current lasing in inversion channel lasers

A new regime of semiconductor laser operation was observed in quantum-well inversion channels of double heterostructure optoelectronic switches. The quantum-well active region operated with substantial excess negative charge imbalance due to the proximity of a high-density depleted donor charge sheet. Threshold current densities as low as 15 A/cm² in as-cleaved 400-μm-long devices were measured, and unusual high-frequency operation under low power operation was observed. These qualities may be of great significance for optical interconnections and optoelectronic integrated circuits     

Recent VLSI neural networks in Japan

In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second).Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.     

Differential optical switching at subnanowatt input power

An operating technique for a differential optical switching device based on a set of parallel-connected pnpn structures is discussed. The differential function at subnanowatt input powers was demonstrated with AlGaAs/GaAs pnpn devices. The highly sensitive devices are promising for applications both to optical neural networks and to optical digital computing because of the low power consumption of the light emitting devices and the large fan-in/fan-out ratio (~10⁵)     

集成电路技术对通信发展的影响

首先说明晶体管和激光管的发明、微电子集成电路、光电子集成和光子集成不断快速进展的情况。于是，叙述几项重要的信息设备技术：（1）处理器、存贮器、计算机；（2）磁盘、光盘、大容量存储；（3）程控交换系统；（4）光纤固定通信网和无线移动通信网。这些重要应用的发展受到集成电路技术的深刻影响，因而能够以惊人速度持续向前跃进。     

Performance comparison between optoelectronic and VLSI multistageinterconnection networks

The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. The bases of the comparison include speed, bandwidth, power consumption, and footprint area. The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2×2 bit-serial switching elements. CMOS technology was used in the VLSI implementation, and it is assumed that the entire network resides on a single chip. Regular free-space optical interconnects are used in the optoelectronic implementation. The results show that for large networks optoelectronics offers higher speed and lower area than VLSI. Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256     

155 Mb/s operation of a FET-SEED free-space switching network

The interconnection problems present in many high-performance digital systems may be alleviated through the use of surface normal optical interconnections using optoelectronic smart pixels. We present recent results of high-speed operation of a five-stage experimental free-space switching network using embedded control techniques for network control. The smart pixels consist of buffered GaAs FET logic with MQW SEED detectors and modulators. The system also incorporates external cavity lasers, bulk, micro, and diffractive optics, two-dimensional fiber bundles, and novel optomechanics. At 155 Mb/s, 77 of the 80 total pixels in the system and 31 of the 32 input fibers were functional. Two of the network paths have carried digital video at 105 Mb/s for over four months without readjustment. Error rate measurements on these paths have shown a short-term BER of 10^-10     

Batch fabrication and structure of integrated GaAs-AlxGa1-xAs field-effect transistor-self-electro-optic effectdevices (FET-SEED's)

The authors have demonstrated a smart pixel prototype field-effect-transistor-self-electrooptic-effect-device (FET-SEED) integrated optoelectronic amplifier utilizing process technology suitable for flexible design and fabrication of high-yield optoelectronic circuits. A single MBE growth sequence provides for quantum-well modulators, photodiodes, doped channel MIS-like field-effect transistors (DMTs), and resistors. The device dimensions are controlled in a planar technology using ion implantation and selective plasma etching for isolation and contacting. Results demonstrate optical amplification in a fully integrated circuit. This technology will enable increased functionality by providing digital electronic processing between optical input and output     

A three-dimensional high-throughput architecture usingthrough-wafer optical interconnect

This paper presents a three-dimensional, highly parallel, optically interconnected system to process high-throughput stream data such as images. The vertical optical interconnections are realized using. Integrated optoelectronic devices operating at wavelengths to which silicon is transparent. These through-wafer optical signals are used to vertically optically interconnect stacked silicon circuits. The thin film optoelectronic devices are bonded directly to the stacked layers of silicon circuitry to realize self-contained vertical optical interconnections. Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated using a standard silicon integrated circuit foundry. These silicon circuits are post processed to integrate the thin film optoelectronics using standard, low cost, high yield microfabrication techniques. The three-dimensionally integrated architectures described herein are a network and a processor. The network has been designed to meet off-chip I/O using a new offset cube topology coupled with naming and renting schemes. The performance of this network is comparable to that of a three-dimensional mesh. The processing architecture has been defined to minimize overhead for basic parallel operations. The system goal for this research is to develop an integrated processing node for high-throughput, low-memory applications     

THE CONTROL, DRIVE AND DISPLAY CIRCUITS ANDDEVICES IN OPTO-ELECTRONIC 2-D PROGRAMMABLE NEURAL NETWORK

In an optoelectronic 2-D programmable neural network system, optical data need to be transferred and feedback with high speed. This paper presents the design and implementation of the interface circuit and its software.     

Rationale and challenges for optical interconnects to electronicchips

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects     

Integrated optical interconnections

The use of optical interconnections between processors, boards, chips, and gates in electronic digital systems to overcome the current performance limitations is described. The advantages of optical interconnections in relation to the interconnection distance, the data capacity, and the interconnection functions are presented. The devices which will support practical implementation of optical interconnections and the integration of optical interconnection devices are discussed. The development of future integrated optoelectronic materials, processing, and fabrication technologies to support integrated optical electronics is also discussed     

Realistic end-to-end simulation of the optoelectronic links andcomparison with the electrical interconnections for system-on-chipapplications

A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption. Realistic end-to-end models of both interconnection schemes are employed in order to evaluate critical performance parameters. A variety of electrical and optoelectronic interconnection configurations are implemented and simulated using accurate optical device and electronic circuit models integrated under an integrated circuit (IC) design computer-aided design tool. Two commercial complementary metal-oxide-semiconductor (CMOS) technologies (0.8 μm and 0.25 μm) are used for the estimation of the signal latency and the power consumption as a function of the interconnection length for the different link configurations. It was found that optoelectronic interconnects outperform their electrical counterparts, under certain conditions, especially for relatively long lines and multichannel data links     

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style

A leakage-tolerant design technique for high fan-in dynamic logic circuits is presented. An NMOS transistor with gate and drain terminals tied together (diode) is added in series with the evaluation network of standard domino circuits. Due to the stacking effect, the leakage of the evaluation path significantly decreases, thereby improving the robustness of the circuit against deep-submicron subthreshold leakage and input noise. To improve the speed of the circuit, a current mirror is also employed in the evaluation network to increase the evaluation current. The proposed technique (diode-footed domino) exhibits considerable improvement in leakage and noise immunity as compared to the standard domino circuits. Simulation results of wide fan-in gates designed using Berkeley Predictive Technology Models of 70-nm technology demonstrate at least 1.9/spl times/ noise-immunity improvement at the same delay compared to the standard domino circuits. Dynamic comparators and multiplexers are designed using the diode-footed domino and conventional techniques to demonstrate the effectiveness of the proposed scheme in improving leakage-tolerance and performance of high fan-in circuits.     

Smart-pixel array technology for free-space optical interconnects

This paper describes a smart-pixel array technology that is being developed at Honeywell for use in chip-to-chip optical interconnections based on free-space optics. The technology combines large-scale, two-dimensional arrays of optoelectronic and microoptical elements with VLSI electronics to enable high-density, high-speed interchip input/output capability in the optical domain. We have demonstrated prototype modules with 16×16 and 32×32 emitter and interleaved detector arrays     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies