SC front-end with wide dynamic range

A novel front-end circuit for capacitive sensors and switched-capacitor (SC) circuits is presented. In this circuit charge is transferred to an input integrator circuit in a controlled way to prevent overload of the input amplifier. Application of this technique extends the linear range for large input signals     

A wide dynamic range continuously adjustable CMOS current mirror

A novel circuit realization of a CMOS current mirror with wide input dynamic range and continuously adjustable gain is presented. The proposed current mirror is linear with respect to signal current in the strong inversion as well as in the subthreshold region of MOSFET operation. The gain is controlled by the same control signal in both regions. The circuit is analyzed using a numerical unified MOSFET model which covers both operating regions. The implemented current mirror is adjustable over more than eight decades of signal current     

Dual-mode wide dynamic range CMOS active pixel sensor

A new dual-mode wide dynamic range CMOS image sensor is designed, which is capable of two different operating modes: logarithmic and floating point mode. The proposed sensor can choose the operating mode manually or adaptively. A prototype pixel is designed and tested with standard 0.5 /spl mu/m CMOS process.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

Digital calibration technique for highly linear wide dynamic range CMOS imaging sensor

A novel digital calibration scheme is developed to improve the linearity of a wide dynamic range (DR) CMOS imaging sensor, with a low calibration overhead. Experimental results show that the distortion of the fabricated imaging sensor reaches -75.6-dB over the 95.3-dB DR after calibration.     

A CMOS circuit for evaluating the NBTI over a wide frequency range

In this paper an application specific integrated circuit (ASIC) for evaluating the NBTI effects over a wide frequency is described. The circuit is designed to allow measurements in multiple modes, specifically, DC and AC NBTI, on single pFET and on an inverter. The results indicate that AC NBTI is independent of the frequency in the 1 Hz–2 GHz range. Furthermore, the voltage and the stress time acceleration are identical for both AC and DC NBTI stress.     

Power analysis and design of wide dynamic range CMOS imaging sensors

Wide dynamic range (WDR) CMOS imaging sensors (CIS) are being designed for new portable, implantable and sensory applications, which demand low power consumption. Compared to normal CISs, high quality WDR CISs generally consume much more power. Up to now, the power consumption of a WDR CIS has never been formally studied. This paper focuses to model and analyze the power consumption of two major WDR CIS designs. Analytical equations are derived for the WDR CIS power, and are verified with HSPICE simulations. The analysis indicates that the power consumption of WDR CISs is dominated by the column bus driving power for large imaging array, while photocurrent related power is negligible. Hence, the WDR CIS power is heavily dependent on the load of the column bus and the read-out frequency. A new partial quantization scheme is developed to acquire WDR images with greatly reduced read-out frequencies. Its power consumption is also analytically derived and verified with HSPICE simulations. A 256×256 partial quantization column consumes about 124.0 nW/pixel in the CMOS process for 16-bit dynamic range and 30 Hz frame rate. The power analysis is further verified by experimental measurements of a proof-of-concept 32×32 partial quantization imaging sensor in the CMOS process.     

A wide dynamic range CMOS PFM digital pixel sensor with in-pixel variable voltage reference

This paper proposes a new pulse-frequency-modulation (PFM) digital pixel sensor (DPS) with a variable reference voltage. An in-pixel variable reference voltage generator is employed to ramp the reference voltage of the comparator locally such that the comparison of photo diode current and the reference voltage can take place earlier. This expands the dynamic range of the pixel sensor when the level of illumination is low. The complexity of routing of the proposed pixel sensor are comparable to that of digital pixel sensor with a constant reference voltage. The additional hardware cost of the proposed digital pixel sensor is only a capacitor and two static inverters, resulting in a fill factor that is comparable to those of digital pixel sensors with a constant global reference voltage. Factors that are critically to the performance of the proposed pixel sensor are examined in detail. The proposed digital pixel sensor has been designed in TSMC-0.18 μm 1.8 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate that the proposed PFM digital pixel has a dynamic range of 120 dB when the integration time is set to 60 μs, approximately 40 dB more than the corresponding PFM digital pixel sensor with a constant reference voltage. The fill factor of the proposed pixel sensor is 20%, comparable to that of pixel sensors with a constant reference voltage.     

A wide dynamic range receiver channel for a pulsed time-of-flightlaser radar

An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed and tested. The bandwidth of the receiver channel is 170 MHz, the transimpedance can be controlled in the range from 1.1 kΩ to 260 kΩ, and the input-referred noise is ~6 pA/√Hz. The distance measurement accuracy is ±4.7 mm (average of 10000 measurements), taking into account walk error (input signal amplitude varies in the range 1:624) and jitter. A considerable increase in the input dynamic range of the receiver has been achieved by placing an integrated current buffer with variable attenuation between the external photodetector and the transimpedance preamplifier. Integrated electronic gain control structures together with the small size and low power consumption achieved by the use of full custom integrated technology considerably simplifies rangefinding devices for many applications. The circuit was implemented in an 0.8-μm BiCMOS process     

A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A low-power wide dynamic range envelope detector

We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.     

A wide dynamic range single-chip SQUID magnetometer

A single-chip SQUID magnetometer is described and demonstrated that integrates a SQUID sensor with feedback circuitry on the same chip. This chip has a very large dynamic range, determined by the sensitivity of the input SQUID and by the current-carrying capacity of the input superconducting lines. This chip can eliminate the need for the sophisticated room temperature circuitry currently used with conventional analog SQUID magnetometers and replace these electronics with a simple bi-directional counter. Furthermore, on-chip multiplexing can be easily implemented for use in multi-channel systems where arrays of more than 100 sensors are required for magnetic imaging. In addition, due to its extremely wide dynamic range and high slew rate, a system based on this chip can be operated in a relatively high magnetic field environment without extensive magnetic shielding     

High frequency wide range CMOS analogue multiplier

A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2 mu m process parameters are given. The circuit has an input range of +or-4 V and linearity error less than 1% for inputs up to +or-3 V. The magnitude and phase response are very flat; even at 30 MHz the change in the magnitude is less than 0.086 dB (1%) and the phase shift is less than 5 degrees .<>     

A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dBdynamic range

A CMOS ΣΔ modulator for speech coding with continuous-time loopfilter is presented. Compared to switched-capacitor implementations, the relaxed bandwidth requirements of the active elements of the loopfilter reduce the power consumption. Furthermore, the need for an antialiasing filter at the modulator input is eliminated. A fourth-order, 64× oversampling ΣΔ modulator for application in portable telephones was designed and shows 80 dB dynamic range over the 300-3400 Hz voice bandwidth. Its input is directly connected to the microphone (maximum 40 mV_RMS). Total harmonic distortion (THD) is below -70 dB at 95 μA current consumption from a 2.2 V supply voltage. The active die area of the modulator is 0.5 mm² in a standard 0.5-μm CMOS process     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

A sigma-delta modulator designed as part of a complete GSM/EDGE (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and low power consumption are the most stringent requirements for the converters in this wireless application. A single-bit 2-2-cascaded modulator operating at 13 MHz has been adopted for high linearity and stability. Low-power low-voltage techniques have been applied along with a top-down design approach in order to minimize the power dissipation. The ΣΔ modulator achieves 13.5 bits of resolution over a bandwidth of 180 kHz while dissipating 5 mW from 1.8-V and 2.4-V supplies. The circuit has been implemented in the CMOS portion of a 0.4-μm (drawn) BiCMOS technology and occupies an active area of 0.4 mm²     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process     

A 12-b, 10-MHz, 250-mW CMOS A/D converter

A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) was implemented using a 0.8-μm p-well CMOS technology. The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm² (4.2 mm×3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than ±0.8 LSB and ±1.8 LSB, respectively