Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.     

A review of board level solder joints for mobile applications

The reliability of electronics under drop-shock conditions has attracted significant interest in recent years due to the widespread use of mobile electronic products. This review focuses on the drop-impact reliability of lead-free solder joints that interconnect the integrated circuit (IC) component to the printed circuit board (PCB). Major topics covered are the physics of failure in drop-impact; the use of board level and component level test methods to evaluate drop performance; micro-damage mechanisms; failure models for life prediction under drop-impact; modelling and simulation techniques; and dynamic stress–strain properties of solder joint materials. Differential bending between the PCB and the IC component is the dominant failure driver for solder joints in portable electronics subjected to drop-impact. Board level drop-shock tests correlate well with board level high speed cyclic bending tests but not with component level ball impact shear tests. Fatigue is the micro-damage mechanism responsible for the failure of solder joints in the drop-shock of PCB assemblies and the fatigue strength of solder joints depends strongly on the strain rate, test temperature, and the sequence of loading. Finally, tin-rich lead-free solders exhibit significantly higher strain rate sensitivity than eutectic SnPb solder.     

圆片级封装技术

圆片级封装(Wafer-LevelPackaging,WLP)已成为先进封装技术的重要组成部分,圆片级封装能够为芯片封装带来批量加工的规模经济效益。在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。综述了圆片级封装的技术及其发展趋势。     

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests.     

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.     

Mechanical behavior of solder joints under dynamic four-point impact bending

Reliability of solder joints under drop impact loading is important to mobile electronic products. In this paper, dynamic four-point impact bending tests of board level electronic packages are carried out to investigate mechanical behavior of solder joints. In the test, strain gauges, a high speed camera and the digital image correlation method are used to acquire strain and deflection of the printed circuit board (PCB). After validated by the test data, a finite element model of the dynamic four-point impact bending test is used to obtain strain and stress in the solder joints. Then, failure predictions of the solder joints are made by strain index, and the predictions are compared with the experimental observations. Furthermore, a strain rate dependent Johnson-Cook material model and rate independent elastic-plastic model of lead-free solder are used to investigate the effect of strain rate on behavior of solder joints under drop impact loading. We find that the material model has insignificant influence on the deflection of the PCB during the drop impact but severely affect the stress and strain in solder joints. The rate independent elastic-plastic solder material model always underestimates the stress and overestimates the strain of the solder joints. The index of equivalent plastic strain computed by the strain rate dependent Johnson-Cook model can predict more realistic failure behavior of the solder joints.     

3D FEM Simulations of Drop Test Reliability on 3D-WLP: Effects of Solder Reflow Residual Stress and Molding Resin Parameters

Numerous three-dimensional (3D) packaging technologies are currently used for 3D integration. 3D-wafer level package (3D-WLP) appears to be a way to keep increasing the density of the microelectronic components. The reliability of 3D components has to be evaluated on mechanical demonstrators with daisy chains before real production. Numerical modeling is acknowledged as a very efficient tool for design optimization. In this paper, 3D finite-elements calculations are carried out to analyze the effects of molding resin’s mechanical properties and thickness on the 3D component’s dynamic response under drop loading conditions. Residual stress generated by solder reflow is also discussed. The influences of residual stresses on the numerical estimation of the component behavior during drop loading are studied. Solder reflow residual stresses have an impact on solder plastic strain and die equivalent stress calculations. We have compared the result of two numerical drop test models. Stress-free initial conduction is introduced for the first model. Solder reflow residual stresses are considered as the initial condition for the second drop test model. Quantitative and qualitative comparisons are carried out to show the effect of residual stress in drop test calculations. For the effect of molding resin thickness on the component behavior under drop loading, the stress-free initial condition is considered. The effect of the molding resin’s thickness on critical area location is discussed. The solder bump maximum plastic shear strain and the silicon die maximum equivalent stress are used as reliability criteria. Numerical submodeling techniques are used to increase calculation accuracy. Numerical results have contributed to the design optimization of the 3D-WLP component.     

Stackable system-on-packages with integrated components

In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Wafer level packaging having bump-on-polymer structure

Kulicke & Soffa’s Flip Chip Division (formerly Flip Chip Technologies), the market leader of wafer level packaging (WLP) technology, has developed a new WLP technology-the Spheron WLP™. Spheron WLP™ was developed with bump-on-polymer structure to decrease the input capacitance for high-speed applications.During development of the Spheron WLP™ technology, a new polymer dielectric material was carefully selected from seven (7) materials that were tested in terms of reliability and manufacturability. The polymer selected demonstrated not only the best reliability but also provided exceptional manufacturability. The favorable mechanical toughness, high elongation, and excellent adhesion to organic and inorganic materials provided excellent performance in reliability tests.     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

An embedded overlay concept for microsystems packaging

An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.     

“电子封装和PCB组装的材料、工艺和可靠性”学术讲座

课程背景 前言：电子产品日益小型化、高功耗和环保要求对电子封装和PCB组装以及材料供应商提出了许多挑战。在这次讲座中我们将详细讲解电子元件封装和PCB组装技术以及工艺，并了解组装材料和工艺对最终产品质量和可靠性的影响。例举并讨论组装材料，例如焊料合金、焊膏、助焊剂和芯片粘接材料的主要特性，及评估认证这些材料和工艺优化的方法。对HoHS和无铅加工技术和可靠性进行深入的探讨。进一步，我们将回顾发生在电子元器件和PCB组装中的主要失效机理。我们将以实际案例来讲解产品可靠性评估，寿命预测，HALT／ESS试验方法。     

“电子封装和PCB组装的材料、工艺和可靠性”学术讲座

课程背景 前言：电子产品日益小型化、高功耗和环保要求对电子封装和PCB组装以及材料供应商提出了许多挑战。在这次讲座中我们将详细讲解电子元件封装和PCB组装技术以及工艺，并了解组装材料和工艺对最终产品质量和可靠性的影响。例举并讨论组装材料，例如焊料合金、焊膏、助焊剂和芯片粘接材料的主要特性，及评估认证这些材料和工艺优化的方法。对HoHS和无铅加工技术和可靠性进行深入的探讨。进一步，我们将回顾发生在电子元器件和PCB组装中的主要失效机理。我们将以实际案例来讲解产品可靠性评估，寿命预测，HALT／ESS试验方法。     

“电子封装和PCB组装的材料、工艺和可靠性”学术讲座

前言：电子产品日益小型化、高功耗和环保要求对电子封装和PCB组装以及材料供应商提出了许多挑战。在这次讲座中我们将详细讲解电子元件封装和PCB组装技术以及工艺，并了解组装材料和工艺对最终产品质量和可靠性的影响。例举并讨论组装材料，例如焊料合金、焊膏、助焊剂和芯片粘接材料的主要特性，及评估认证这些材料和工艺优化的方法。对HoHS和无铅加工技术和可靠性进行深入的探讨。进一步，我们将回顾发生在电子元器件和PCB组装中的主要失效机理。我们将以实际案例来讲解产品可靠性评估，寿命预测，HALT／ESS试验方法。     

LCCC封装器件热疲劳失效分析及结构优化研究

针对LCCC封装器件在温度循环载荷下焊点开裂的问题,首先分析其失效现象和机理,并建立有限元模型,进行失效应力仿真模拟。为降低焊点由封装材料CTE不匹配引起的热应力,提出了两种印制板应力释放方案,并分析研究单孔方案中不同孔径和阵列孔方案中不同孔数量对热疲劳寿命的影响。之后,为降低对PCB布局密度的影响,提出一种新型的叠层焊柱应力缓冲方案,进行了不同叠层板厚度和焊柱间距的敏感度分析。结果表明,更大的开孔面积、更小的叠层板厚度、更密的焊柱可有效降低焊点应力,提高焊点热疲劳寿命,使得LCCC封装器件焊点热疲劳可靠性得到有效提高。     

28 nm WLP封装中PBO结构对CPI可靠性的影响

基于28 nm晶圆级封装(WLP)工艺,研究了聚苯撑苯并噁唑(PBO)对芯片-封装交互(CPI)可靠性的影响,分析了PBO堆叠关系和边缘位置的选择对CPI可靠性的影响.仿真实测结果表明,堆叠关系和边缘位置的变化对CPI可靠性有较显著的影响,两种因素的失效机理不同.利用TCAD工具能够有效预测结构变更对CPI可靠性的影响...     

同一PCB板上不同封装结构的热应力分析

基于ABAQUS有限元分析软件,对同一PCB板上QFP和PBGA两种不同封装结构,在温度循环载荷下的应力场进行了研究,并对不同封装结构的性能进行了比较分析。结果表明:在温度循环载荷下,无论何种封装组件,越靠近PCB板的边缘,器件的应力值越大;在同等条件下,PBGA封装器件的应力值高于QFP封装器件;以同类封装器件中最大应力值的10%为临界点,封装器件中应力值比最大应力值小10%以上的为非薄弱元器件,其余均定义为薄弱元器件。根据该定义,对前述5组QFP和PBGA封装器件,除位于PCB板中间位置的外,其余各组封装器件均为薄弱元器件。     

Vibration reliability characterization of PBGA assemblies

Generally, the low-cycle fatigue induced by thermal cycling is the major concern in the reliability of surface mount technology for electronic packaging, but the high-cycle fatigue induced by vibration can also contribute significant effect, especially for applications in automobile, military, and avionic industries. To assess vibration induced fatigue failures, the dynamic properties of printed circuit board (PCB) assemblies play a very important role. In this paper, the dynamic properties of a plastic ball grid array (PBGA) assembly were characterized by using experimental modal testing and finite element analysis. The bare PCB and PCB assembly with PBGA modules mounted were tested and analyzed separately, so that the influence of PBGA modules on the PCB’s dynamic properties could be identified. It was found that mounting PBGA modules to PCB increased the stiffness of the PCB. Results of constant-amplitude vibration reliability testing of the PBGA assembly are also reported. It was found that the PBGA assembly was vulnerable to vibration, and fatigue failure always occurred at the corner solder balls of the PBGA module.