Plasma-enhanced flexible metal-insulator-metal capacitor using high-k ZrO2 film as gate dielectric with improved reliability

We demonstrate a new flexible metal-insulator-metal capacitor using 9.5-nm-thick ZrO₂ film on a plastic polyimide substrate based on a simple and low-cost sol-gel precursor spin-coating process. The surface morphology of the ZrO₂ film was investigated using scan electron microscope and atomic force microscope. The as-deposited ZrO₂ film under suitable treatment of oxygen (O₂) plasma and then subsequent annealing at 250 °C exhibits superior low leakage current density of 9.0 × 10⁻⁹ A/cm² at applied voltage of 5 V and maximum capacitance density of 13.3 fF/μm² at 1 MHz. The as-deposited sol-gel film was completely oxidized when we employed O₂ plasma at relatively low temperature and power (30 W), hence enhancing the electrical performance of the capacitor. The shift (Zr 3d from 184.1 eV to 184.64 eV) in X-ray photoelectron spectroscopy of the binding energy of the electrons towards higher binding energy; clearly indicates that the O₂ plasma reaction was most effective process for the complete oxidation of the sol-gel precursor at relatively low processing temperature.     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

Facile polymer gate dielectric surface-modification for organic thin-film transistors using self-assembled surfactant layer

We demonstrate facile polymer gate dielectric surface-modification method for organic thin-film transistors (OTFTs). We simply introduce self-assembled surfactant layer onto the top surface of poly(4-vinylphenol) (PVP) dielectric by spin coating PVP solution mixed with sodium dodecyl sulfate and tridecafluorohexane-1-sulfonic acid potassium salt as additive agents. The surfactant-modified PVP layer acquires various merits compared to pristine PVP layer in terms of surface smoothness and hydrophobicity, as confirmed by contact angle measurement, atomic force microscopy analyses, grazing incident X-ray diffraction and near-edge X-ray absorption fine structure spectroscopy. The resulting OTFTs with the conventional semiconducting poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b]thiophene) as the active layer and surfactant-modified PVP as the dielectric layer reveal overall ascendency over the OTFT with pristine PVP, especially in terms of operating hysteresis and reliability. The effects of hydrophobicity of surfactants on the surface properties of PVP as well as the OTFT performances are fully discussed in conjunction with various characterization tools.     

聚酰亚胺为栅绝缘层的并五苯场效应晶体管

以真空蒸发的有机半导体材料并五苯为有源层,以旋涂的聚酰亚胺作为栅绝缘层,以真空蒸发的Al为栅、源和漏电极,成功制作了顶接触式并五苯有机场效应晶体管(OFET).测试表明,在源漏电压为70 V时,器件的载流子迁移率μ为0.079 cm2/V·s,器件的开关电流比为1.7×104.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

Fabrication of pentacene organic field-effect transistors with polyimide gate dielectric layer

The organic field effect transistors had been fabricated using the pentacene by vacuum evaporation as the active layer, the polyimide by spin coating as insulator layer, and aluminum by vacuum evaporation as gate, source and drain electrodes respectively. The field-effect mobility of 0.079 cm2/V.s was tested at Vds=70 V, and on/off radio up to 1.7×104.     

外延CeO2高k栅介质层的结构及介电性能

利用脉冲激光沉积两步生长法在Si(111)衬底上制备了厚度为10～40nm的外延CeO<,2>薄膜,构建了Pt/CeO<,2>/Si MOS结构.研究了CeO<,2>薄膜的界面及介电性能,实验发现,界面处存在的电荷对MOS结构C-V特性的测量有较大影响,采用两步生长法制备的外延CeO<,2>薄膜在保持较大介电常数的同时...     

Flexible complementary inverter with low-temperature processable polymeric gate dielectric on a plastic substrate

We report low-temperature processability of poly(4-vinylphenol) based gate dielectric by investigating the effect of composition and processing temperature on the thermal, mechanical and electrical characteristics of the gate dielectric. We found that the processing temperature of the gate dielectric could be reduced up to 70 °C by optimizing the composition of the gate dielectric solution. Based on this finding, we have fabricated a flexible organic complementary inverter by integrating n- and p-type organic thin-film transistors (OTFTs) with the low-temperature processable gate dielectric on a plastic substrate. Pentacene and F16CuPc were used as p-type and n-type semiconductor, respectively. The inverter shows that the swing range of V_out is same as V_DD, which ensures “zero” static power consumption in digital circuits. The logic threshold of the inverter with G5 gate dielectric cured at 70 °C is 21.0 V and the maximum voltage gain (∂V_out/∂V_in) of 8.1 is obtained at V_in = 21.0 V. In addition, we have discussed in more detail the characteristics of the OTFTs and the complementary inverter with respect to the process condition of the gate dielectric.     

Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

In the present study, a technology for the formation of a submicron GaAs MESFET gate of 0.5–0.1 μm in length and above 0.5 μm in height using a four-layer dielectric dummy gate was developed. Techniques of chemical and plasma-chemical deposition from a gaseous phase, differing in etch rates in a buffer solution of hydrofluoric acid, were used to prepare silicon oxide films. Different constructions of a multilayer structure with varying sequences of layers and thicknesses were studied. The conditions of chemical and plasma-chemical etching of dielectrics allowing a dummy double-T-gate to be formed were determined. The employment of a sophisticatedly shaped dummy gate made it possible to obtain a gate electrode of a large cross section with a low length. The possibility in principle to fabricate a MESFET gate with a length of up to Lg = 0.1 μm using lithographic procedures with a minimal resolution of 1.0 μm was demonstrated.     

Parylene based bilayer flexible gate dielectric layer for top-gated organic field-effect transistors

In this paper, we report on a bilayer insulating film based on parylene-c for gate dielectric layers in top-gate/bottom-contact inkjet-printed organic field-effect transistors (OFETs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and poly([N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bitthiophene)) (P(NDI2OD-T2)) as with p- and n-channel semiconductors. The thin parylene-c film (t = 210 nm) show large gate leakage density (2.52 nA/cm² at 25 V) and low breakdown voltage (2.2 MV/cm). In addition, a degraded field-effect mobility (μ) was observed in printed IDTBT and P(NDI2OD-T2) OFETs with the parylene-c single-layered dielectric. X-ray photoelectron spectroscopy (XPS) analysis reveals that the degradation of μ is due to unwanted chemical interaction between parylene-c and the conjugated polymer surface during the parylene-c deposition process. By inserting 50-nm thick poly(methyl-methacrylate) (PMMA) and polystyrene (PS) layer in-between the parylene-c and conjugated polymer film, highly improved gate leakage density and breakdown voltage are achieved. The printed IDTBT and P(NDI2OD-T2) OFETs with a bilayer dielectric compose of parylene-c and PMMA and PS show significantly improved hole and electron μ of 0.47 cm²/Vs and 0.13 cm²/Vs, respectively, and better operation stability. In addition, we demonstrate inkjet-printed polymer complementary inverter with a high voltage gain of 25.7 by applying a PS/parylene-c bilayer dielectric.     

SrHfO3 as gate dielectric for future CMOS technology

Thin epitaxial films of the high-κ perovskite SrHfO₃ were grown by molecular beam epitaxy on Si(100) and investigated by ellipsometry and X-ray photoelectron spectroscopy to determine its band gap and valence band offset. Conducting AFM shows a good correlation between topography and current mapping, pointing to direct tunneling conduction. Long channels MOSFETs with low equivalent oxide thickness (EOT) were fabricated and their channel mobility measured. Mobility enhancement can be achieved by post processing annealing in various gases but at the cost of interfacial regrowth. An alternative approach is to increase mobility without changing EOT is by electrically stressing the gate dielectric at ∼150 °C.     

Electrophotographic processes using a dielectric layer bonded to a photoconductive layer as in the Katsuragawa process

With a photosensitive plate having a dielectric overcoating, an electrophotographic process available for repeated operation is developed. This process consists of three steps, utilizing the effect of photopolarization. An important feature is to allow the employment of higher photoconductive layers. As a result, high photosensitivity and high electrostatic contrast in electrophotography are achieved with this process. Factors determining the sensitivity are the rate of dark depolarization and light polarization and, in addition, the corona charging rate. This process may make possible applications in fields where only a slight exposure is allowed. What occurs in each step of this process is investigated analytically and experimentally.     

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.     

Starch as ion-based gate dielectric for oxide thin film transistors

Application of nature bio-materials in electronics represents an emerging field of science and technology that began a few years ago. For the dielectric of transistors, the ion-based electric double layer (EDL) gating has becoming the widely accepted theory of charge modulation with hydrated bio-polymer dielectrics. Herein, we report on the use of starch as the ion-based gate dielectric for oxide thin film transistors. Two types of starches, i.e., water-soluble starch and potato starch were studied either with or without the incorporation of glycerol. Important parameters including mechanical strength, surface morphology, specific capacitance and ion conductivity were analyzed in accordance with the molecular structure of starches. The transistor performance was found in close relation with the specific capacitance and ion conductivity of the starch dielectrics. Higher on/off ratio (2.6 × 10⁶) and field mobility (0.83 cm²V⁻¹s⁻¹) were obtained with glycerol incorporated potato starch due to the advantage in capacitance and ion conductivity. Lower ion conductivity of the water-soluble starch on the other hand caused the large current hysteresis, so the current retention property was examined for the potential application as a memory element. Collectively, this work solidifies our knowledge on the material type, EDL gating mechanism and applicability of nature bio-material gated transistors.     

A protecting layer for the dielectric in AC plasma panels

One of the important problems in the development of ac plasma panels is to produce panels that maintain stable characteristics for a long time. A new idea for using a protecting layer over the dielectric layer which isolates the electrodes from the gas was examined and good results were obtained. Moreover, besides stability, a considerable improvement of operating characteristics was achieved, including low-voltage operation capability. Sputtering of the protecting layer, which is thought to govern the life of plasma panels, occurs even to heat-resisting oxides of large binding energy, but the sputtering rate appears to be so slow that it hardly affects the panel life. Also, the rate of decomposition accompanying sputtering is small. The problem of cracks in the protecting layer, which is the cause of defective life characteristics in such respects as migration of the lead component of the dielectric layer onto the protecting layer and the direct exposure of the dielectric-layer glass to the discharge, was solved by process-technique improvements. This paper describes the merit of using a protecting layer, required performance for this layer, and experimental results, and discusses voltage stability and the results of selection of materials for it.     

Thermal and plasma enhanced atomic layer deposition ruthenium and electrical characterization as a metal electrode

Ruthenium thin films were grown by thermal and plasma-enhanced atomic layer deposition (PE-ALD) using O₂ and ammonia (NH₃) plasma, respectively. RuCp₂ and Ru(EtCp)₂ were used as Ru precursors. Pure and low resistivity (<20 μΩ cm) Ru films were grown by PE-ALD as well as thermal ALD. PE-ALD Ru showed no nucleation delay on various substrates including TaN_x, Si, and SiO₂, in contrast to thermal ALD Ru. And the root-mean-square (RMS) roughness of PE-ALD Ru was lower than that of thermal ALD Ru. Additionally, metal-oxide-semiconductor (MOS) capacitor composed of p-Si/ALD Ta₂O₅/ALD Ru (35 nm) was fabricated and C-V measurements were performed for as-deposited sample. Very small hysteresis of 20 mV was obtained, and effective work function difference to Si substrate was minimal as −0.03 V. For comparison, MOS capacitor was fabricated using sputtered Ru and large hysteresis of 0.5 V and flat band voltage (V_FB) shift to negative value were observed. This result indicates that ALD process produces more reliable, damage free Ru gate compared to sputtering process.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

Using simple physical models, specific relationships between parameters measured by X-ray photoelectron spectroscopy (XPS) and those measured on MOS transistors are described for silicon oxynitride gate dielectrics prepared by plasma nitridation. Correlations are established between the equivalent oxide thickness (EOT) and gate leakage current and the nitrogen anneal dose and physical thickness as measured by XPS. These correlations, from devices in the 10 to 13 /spl Aring/ EOT range, allow accurate estimates of electrical thickness and leakage without device fabrication, enabling both development and process monitoring for sub-130-nm node gate dielectrics.