BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an IEEE 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an IEEE 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch.To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional IEEE 1149.1 and IEEE 1500 standards.     

An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture

This paper presents an implementation approach for the test of routers in a fine grain massively parallel architecture. First, an ad hoc test technique which diffuses test messages router by router is analyzed. Even though the technique does not add hardware, it is shown inefficient and not applicable due to practical constraints such as the limited number of pins of the chip implementing the machine. Based on a hierarchical implementation of the IEEE 1149.1 standard, two approaches are proposed and compared in terms of the area overhead, the overall test time and the flexibility in applying tests and diagnosing the routers inside the machine. The basic idea for both approaches is to construct groups of basic cells which are driven by the same test block and compare their test results after the same test vectors are applied at each cell input. The two approaches differ in the granularity of a basic cell. The choice of an implementation approach is not trivial. It is shown that each approach presents better performance than the other, that is, the approach which allows better fault coverage and less test time requires more silicon and less diagnostic possibilities compared to the second approach.     

基于IEEE1149.7的新一代测试接口实现与应用

随着芯片集成度的不断增加和对低功耗设计的重视,原初开发的JTAG（IEEE STD1149.1）面对新的挑战,不能满足当今设计的需要。CJTAG基于IEEE STD1149.7标准和传统的JTAG的边界扫描原理来提供一个更加强大的测试和调试的标准,来达到现在系统的要求。CJTAG用更少的管脚来提供更多的功能,而同时保证了对IEEE1149.1的软件和硬件的兼容性。     

NoC功耗与性能的研究

在当前高性能片上网络设计中,功耗和延迟是设计所面临的核心问题之一。在此着重阐述了构成低功耗和低延迟NoC的4种结构:低摆幅的信号传输结构、可重构的NoC结构、3D的IC设计结构、基于数据压缩机制的结构。通过对其功过原理的分析,比较了4种结构的优缺点,最后对未来低功耗、低延迟的NoC发展方向做出了预测。     

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output. Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Micro-electronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing, and low power testing. He has authored and co-authored more than 90 papers on these fields, and has supervised several PhD dissertations. He has also participated to several European research projects (Esprit III ATSEC, Eureka MEDEA, MEDEA+ ASSOCIATE, IST MARLOW). Patrick GIRARD holds a B.Sc. and a M.Sc. in Electrical Engineering, and obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992. Olivier Héron is presently researcher at CEA (French Center for Technology Research) in the laboratory of Reliability for Embedded Systems. His research interests are Logic BIST, On-Line Testing, Delay Fault Testing of FPGAs and Fault Modelling. He is a member of the program commitee of the Field Programmable Logic Conference FPL2006. He received his Ph.D. from the University of Montpellier (France) in 2004 and worked in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He received the B.Sc. degree in 1998 and the M.Sc. degree in 2001 in Electrical Engineering from the University of Montpellier. Serge Pravossoudovitch was born in 1957. He is currently Professor in the Electrical and Computer Engineering Department of the University of Montpellier and his research activities are performed at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier—France). He is received the Master degree in Electrical Engineering in 1979 from the University of Montpellier. He got his Ph.D. degree in Electrical Engineering in 1983 on symbolic layout for IC design. Since 1984, he was been interested in the testing domain. He obtained the “doctorat d’état” degree in 1987 for his works on switch level automatic test pattern generation. He is presently interested in delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, MEDEA). Michel Renovell is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee) and Chair of the FPGA testing Committee. He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of several conferences: International Mixed Signal Testing Workshop IMSTW2000, Field Programmable Logic Conference FPL2002 and European Test Symposium ETS2004. A preliminary version of this work has been presented at the 1st European Test Symposium 2004, in Ajaccio.     

基于硬件时间戳的IEEE1588时间同步技术的一种实现方法

本文简要分析了IEEE1588协议的时间同步原理,从工程实践的角度提出了一种基于现场可编程逻辑门阵列(FPGA)的IEEE1588时间同步技术的实现方法,给出了实现方案和框图。重点分析了采用FPGA实现硬件时间戳的方法,并给出相应的仿真结果。     

IEEE 1588协议在光通信网络中的研究与应用

通过对IEEE 1588精密时间同步协议及SDH(Synchronous Digital Hierarchy)协议的研究,介绍了一种在光通信网络上实现网络时间精确同步的方法.同时也指出1588精密时间同步协议是替代光通信网络传统GPS时间同步方案的发展方向.     

Survey of multi-channel MAC protocols for IEEE 802.11-based wireless Mesh networks

This paper reviews multi-channel media access control (MAC) protocols based on IEEE 802.11 in wireless Mesh networks (WMNs). Several key issues in multi-channel IEEE 802.1l-based WMNs are introduced and typical solutions proposed in recent years are classified and discussed in detail. The experiments are performed by network simulator version 2 (NS2) to evaluate four representative algorithms compared with traditional IEEE 802.11. Simulation results indicate that using multiple channels can substantially improve the performance of WMNs in single-hop scenario and each node equipped with multiple interfaces can substantially improve the performance of WMNs in multi-hop scenario.     

基于FPGA的IEEE 1394链路层控制器的设计与实现

阐述了IEEE 1394总线的工作原理与链路层控制器的设计方案,并以Altera公司的Cyclone系列FPGA为平台,给出了IEEE 1394链路层控制器的逻辑设计、功能仿真和电路验证。实验表明,该控制器芯片达到了100Mbit/s的传输速度,符合IEEE 1394规范。     

IEEE1394接口用LSI的近期动向

随着配备ＩＥＥＥ１３９４接口的设备的增加,自１９９９年下半年起,ＩＥＥＥ１３９４接口用ＬＳＩ的价格开始大幅度下降。锭路层ＬＳＩ正积极引入防复制技术并向定制化方向发展;物理层ＬＳＩ的目标则主要是实现低功耗化。此外,一些主要的半导体制造商的开发重点已瞄准了面向下一代标准－Ｐ１３９４ｂ的ＬＳＩ。     

基于IEEE802.15.4的Ad Hoc网络快速组网研究

IEEE802.15.4是一种低功耗的无线网络通信协议标准,适用于能量有限的无线网络中。提出了一种基于IEEE802.15.4标准的低功耗、能够快速组网的Ad Hoc网络组网方案。在该组网方案中,以IEEE 802.15.4协议标准为基础,设计了一个能够快速组网的网络层。在网络层中,使用AODV作为Ad Hoc网络的路由协议。     

基于IEEE1588v2协议的光网络时间同步技术研究

分析了现有光网络中时间同步实现方法的不足,阐述了IEEE 1588v2协议的基本原理,提出了IEEE 1588v2协议在光通信网络中实现时间同步的方法,指出精确时间同步协议在光网络中的应用前景和发展方向.     

一种针对IEEE 802.15.4a网络监听仪的设计

针对最新国际标准IEEE802.15.4a的工业无线网络环境,提出了一种应用于该网络的监听仪(即sniffer)。首先介绍了它的工作原理,并与传统网络中监听仪作简要对比;其次设计了系统的软硬件结构;最后该监听仪在基于IEEE802.15.4a标准平台的CSMA/CA协议和WICN-Z协议的无线传感器网络中实现了对节点之间数据的嗅探监听,经实验测试,结果表明:监听仪能有效检测网络的运行状态。     

基于边界扫描技术的SOC数字电路可测性设计

随着SOC系统的快速发展,如何对其进行有效的测试与诊断是当前研究的热点问题。从SOC数字电路可测试性设计的角度出发,基于边界扫描技术,设计了具有边界扫描结构的IP核,并对相应的测试方法进行了研究。通过仿真及时序分析,验证了该设计方法的可行性,为SOC系统的测试提供了新的思路。     

一种PTN网络中IEEE 1588v2非对称时延的解决方案

针对IEEE 1588v2协议双纤双向传输的非对称时延问题,采用粗波分复用技术实现主从端的精确时间同步,解决了非对称时延问题。分析了色散、折射率和温度等因素对单纤双向传输时延的影响,给出了实现精确时间同步的试验方案,并在中国移动的PTN现网中进行了试验。结果表明,采用该方法不仅能够达到时间同步的精度要求,而且可以节省光纤。     

面向工业物联网的IEEE 802.11ah协议RAW在线式重分组方法

针对标准RAW机制无法适应网络环境变化做出调整,且分组依赖连续的AID问题,提出一种基于伪随机序列的RAW重分组方法。AP在关联阶段为节点分配一个伪随机序列作为地址码,在分组阶段采用分组复合码携带分组信息。该方法实现了非连续AID节点在线式重分组,减小了重分组的时间开销。为使RAW合理分配资源,解决组间负载不平衡问题,提出了基于期望信道时间的RAW重分组方法,以信道利用率为分组依据,优化了节点RAW组、RAW持续时间和RAW分组数。NS3仿真结果表明,所提方法显著提高了IEEE802.11ah协议的网络性能。     

一种基于IEEE802.11EDCF的自适应能量调整算法

简述了IEEE802.11及IEEE802.11e的两种访问控制机制DCF和EDCF,提出了一种基于IEEE802.11 EDCF的自适应能量调整算法,并在NS2上进行了仿真实现.仿真实验结果表明,该算法能够根据分组的优先权水平和节点当前能量值动态调度信道接入,延长了全网的生存期.     

基于连接两段激活模型的IEEE 802.16接纳控制算法

IEEE802.16系统中数据的传输是面向连接的,连接的建立服从两段激活模型。针对系统空闲资源耗尽但还为已接纳而未被激活的业务预留资源这一情况,该文提出了一种适当借用此预留资源去接纳新的立即被激活业务的接纳控制算法,并建立了此算法的3维马尔可夫链模型,进行了理论分析提出了找寻此算法中使用的两个门限的搜索方法。仿真结果表明,该接纳控制算法能显著地降低新业务阻塞率,提高系统的带宽利用率,已接纳业务的激活成功率只有少许下降。     

An enhanced MAC protocol based on the IEEE 802.11 for data relay satellite systems

Data relay satellite (DRS) systems play an important role in space information networks. Characterized by highly dynamic topology and discontinuous communication links, it is suggested that the IEEE 802.11 protocol employed in such a network could be more flexible. However, such a terrestrial network protocol could not be applied to DRS systems directly, nor supports a fast response due to the long propagation delay and severe packet collision. To address this challenge, we proposed an enhanced media access control (MAC) protocol based on the IEEE 802.11 protocol providing multiaccess for low earth orbit (LEO) distributed constellations. In this paper, we investigated the access delay performance of the proposed protocol in our model. Then, we derived a contention window adaption by using an iteration algorithm that can dynamically adjust the values of the contention window depending on the number of user satellites in the communication coverage. Simulation results show that the average access delay does not exceed 20 seconds, which is significantly lower than the standard protocol. Moreover, the traffic threshold is increased to 0.6, and the maximum throughput has doubled compared with the standard protocol. It is proved that the enhanced MAC protocol shows a better performance in DRS systems.     

An efficient admission control for IEEE 802.11 networks based on throughput analyses of (un)saturated channel

This paper presents a novel analytical model and an efficient admission control (AC) algorithm for IEEE 802.11 distributed coordinated function access mechanism. In contrast to the previous approaches, both saturated and unsaturated states of network are analyzed and the impacts of error‐frame rate and retransmission limit are also taken into account based on an improved Markov chain model. Thus, the network resources can be efficiently utilized. Taking the throughput difference between saturated and unsaturated states as the residual bandwidth, an efficient AC algorithm is designed to utilize the network resources effectively. Extensive simulation data match our analytical results and demonstrate that the AC algorithm is efficient and can make the effective utilization of network resources. Copyright © 2008 John Wiley & Sons, Ltd.