共查询到20条相似文献,搜索用时 15 毫秒
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为了自动快速地分析微处理器对软错误的敏感性,该文提出一种基于FPGA故障注入的软错误敏感性分析方法。在FPGA芯片上同时运行有故障和无故障的两个微处理器,并充分利用FPGA的并行性,把故障注入控制、故障分类、故障列表等模块均在硬件上实现,自动快速地完成全部存储位的故障注入。以PIC16F54微处理器为实验对象,基于不同负载分别注入约30万个软错误用以分析微处理器软错误敏感性,并对敏感性较高的单元加固后再次进行分析,验证该方法的有效性。实验数据表明,使用该方法进行故障注入及敏感性分析所需的时间比软件仿真方法提高了4个数量级。 相似文献
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《Microelectronics Reliability》2015,55(1):24-30
Soft errors due to neutrons and alpha particles are among the main threats for the reliability of digital circuits operating at terrestrial level. These kinds of errors are typically associated with SRAMs and latches or DRAMs, and less frequently with non-volatile memories. In this paper we review the studies on the response of NAND and NOR Flash memories to ionizing particles, focusing on both single-level and multi-level cell architectures, manufactured in technologies down to a feature size of 25 nm. We discuss experimental error rates obtained with accelerated tests and identify the relative importance of neutron and alpha contributions. Technology scaling trends are finally discussed and modelled. 相似文献
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Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90 nm CMOS technology. Under 22 nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance. 相似文献
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The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach. 相似文献
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《Microelectronics Reliability》2014,54(6-7):1412-1420
Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead. 相似文献
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基于静态随机存储器的现场可编程逻辑门阵列应用于航天电子系统时,易受到单粒子翻转效应的影响,存储数据会发生损坏。为评估器件和电路在单粒子翻转效应下的可靠性,提出一种基于TCL脚本控制的故障注入系统,可在配置码流层面模拟单粒子翻转效应。介绍了该故障注入系统的实现机制和控制算法,并将该软件控制方法与传统硬件控制方法进行对比分析。设计了一种关键位故障模型,从设计网表中提取关键位的位置信息,缩小了故障注入的码流范围。在Virtex-5开发板XUPV5-LX110T上的故障注入实验表明,该故障注入系统能有效模拟单粒子翻转效应,与传统随机位故障注入相比,关键位故障注入的故障率提高了近5倍。 相似文献
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《Microelectronics Reliability》2015,55(1):264-271
Shrinking the transistors size and supply voltage in the advanced VLSI logic circuits, significantly increases the susceptibility of the circuits to soft errors. Therefore, analysis of the effects on other nodes, caused by the soft errors occurring at each individual node is an essential step for VLSI logic circuit design. In this paper, a novel approach based on the Mason’s gain formula, for the node-to-node sensitivity analysis of logic circuits is proposed. Taking advantage of matrix sparsity, the runtime and the memory requirement of the proposed approach become scalable. Also, taking the effects of reconvergent paths into account, the accuracy of the proposed approach is improved considerably. According to the simulation results, the proposed approach runs 4.7× faster than those proposed in the prior works while its computational complexity is O(N1.07) on the average. 相似文献
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MPEG-2视频信号错误控制和错误掩盖技术 总被引:3,自引:0,他引:3
以MPEG-2的语法规范作基础,从控制错误发生和控制错误传播的角度,简述了MEPG-2的分级工具和视频码流层结构,比较详细地介绍了I帧、P帧和B帧的错误掩盖技术,此外,还推荐了一些错误掩盖方法。 相似文献
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Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of the sequential circuits to SEUs is an important consideration in nanoscale near threshold CMOS design. This paper presents an energy efficient SEU tolerant latch. The proposed latch improves the SEU tolerance by using a clocked Muller- C and memory elements based restorer circuit. The parasitic extracted simulations using STMicroelectronics 65 nm CMOS technology show that by employing the proposed latch, an average improvement of ∼40% in energy delay product (EDP), is obtained over the recently reported latch. Moreover, the proposed latch is also validated in a TCAD calibrated PTM 32 nm framework and PTM 22 nm CMOS technology nodes. In 32 nm and 22 nm technologies, the proposed latch improves the EDP ∼12% and 59% over existing latches respectively. 相似文献
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分析了 CMOS数字专用集成电路功耗的来源,给出了半定制数字专用集成电路功耗的计算方法以及功耗优化设计的方法。 相似文献
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The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A few additional steps during logic synthesis and layout generation have been introduced in order to implement the redundant net-lists and power domains as well as to place the latchup protection switches. The approach and accompanying techniques have been verified on the example of a shift-register and a middleware switch processor. 相似文献
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介绍了ASIC设计过程中测试矢量的产生与验证步骤,包括激励编写规划、波形检查、测试矢量的获得以及测试矢量的验证。 相似文献
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FPGA器件在航天领域应用广泛,然而在空间环境下,基于SRAM工艺的FPGA器件极易受到单粒子翻转(Single Event Upsets,SEU)影响而导致电路发生软错误。针对具有代表性的Xilinx Virtex系列器件进行了SEU评估方法的研究,设计并开发了一款面向Virtex器件的SEU效应评估工具,并与FPGA标准设计流程进行了有效融合。实验结果表明,提出的评估方法和工具对Virtex器件的SEU效应可以进行准确的评估,从而为FPGA结构设计和应用开发提供先于硬件实现的软件验证环境,对高可靠性FPGA芯片的研究、开发和设计都具有重要意义。 相似文献
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This paper proposes a new switch box architecture in SRAM-based FPGAs to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch box is reduced to 67% without any impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The architecture was evaluated on several MCNC benchmarks using the VPR tool. Experimental results show that this architecture decreases the susceptibility of switch boxes to SEUs by about 20% on average compared to the traditional ones. 相似文献
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Accelerated assessment of fine-grain AVF in NoC using a Multi-Cell Upsets considered fault injection
《Microelectronics Reliability》2014,54(11):2629-2640
With the increasing threat of soft errors induced bits upset, Network on Chip (NoC) as the communication infrastructure in many-core systems has been proven a reliability bottleneck in a fault tolerant parallel system. The often-used metric Architecture Vulnerability Factor (AVF), measures the architecture-level soft error impacts to compromise the design cost of fault tolerant schemes and reliability well. As a complementary of existing estimation methods about standard IP like processor and Cache, this work aims at an accelerated fault injection methodology for the fine-grain AVF assessment in NoC via two components: (1) modeling the complex fault patterns of both Multi-Cell Upsets (MCU) and Single Bit Upset (SBU) in the standard Fault Injection (FI) method; (2) accelerating the estimation via classifying and exploiting the fine-grain metrics according to different error impacts. The comprehensive simulation results using the diverse configures (e.g., varying fault model, benchmark, traffic load, network size and fault list size) also demonstrate that the proposed approach (i) shrinks the estimation inaccuracy due to MCU patterns 18.89% underestimation in no protection case and 88.92% overestimation under ECC (Error Correction Coding) protection on average; (ii) achieves about 5× speedup without estimation accuracy loss via phased pre-analysis based on fine-grain classification; (iii) verifies ECC a cost-effective mechanism to protect NoC router: soft errors reduced by about 50% over the no protection case, with only less than 2% area overhead. 相似文献
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深亚微米ASIC设计中的时序约束与静态时序分析 总被引:2,自引:0,他引:2
在现代深亚微米专用集成电路(ASIC)设计流程中,为使电路性能达到设计者的预期目标,并满足电路工作环境的要求,必须对一个电路设计进行诸如时序、面积、负载等多方面的约束,并自始至终使用这些约束条件来驱动电路设计软件的工作.文中介绍了设计中所需考虑的各种时序约束,并以同步数字系列(SDH)传输系统中8路VC12-VC4 E1映射电路设计为例,详细说明了设计中所采用的时序约束,并通过静态时序分析(STA)方法使电路时序收敛得到了很好的验证. 相似文献