A fast,flexible, and easy-to-develop FPGA-based fault injection technique

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities of Altera FPGAs in order to inject single event upset (SEU) and multiple bit upset (MBU) fault models in both flip-flops and memory units. As this technique uses FPGA built-in facilities, it imposes negligible performance and area overheads on the system. The experimental results show that the proposed technique is on average four orders of magnitude faster than a pure simulation-based fault injection. These features make the proposed technique applicable to industrial-scale circuits.     

Interval methods for fault-tree analysis in robotics

This paper describes a novel technique, based on interval methods, for estimating reliability using fault trees. The approach encodes inherent uncertainty in the input data by modeling these data in terms of intervals. Appropriate interval arithmetic is then used to propagate the data through standard fault trees to generate output distributions which reflect the uncertainty in the input data. Through a canonical example of reliability estimation for a robot manipulator system, we show how the use of this novel interval method appreciably improves the accuracy of reliability estimates over existing approaches to the problem of uncertain input data. This method avoids the key problem of loss of uncertainty inherent in some approaches when applied to noncoherent systems. It is further shown that the method has advantages over approaches based on partial simulation of the input-data space because it can provide guaranteed bounds for the estimates in reasonable times     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects

Due to shrinking feature size and higher transistor count in a single chip in modern fabrication technologies, power consumption and soft error reliability have become two critical challenges which chip designers are facing in new silicon integrated circuits. Recent studies have shown that these issues have compromising effects on each other. Besides, power consumption and reliability significantly vary across workloads and among pieces of a single application which can be exploited to design adaptive runtime fault tolerant and low power systems. These attractions have been exploited in prior studies to design online reconfigurable fault tolerant systems with power management schemes. However, those attempts are driven by complicated simulations and hardly deliver a sense of direction to the designers. To achieve maximum efficiency in terms of power, performance, and reliability in dynamic scaling of voltage and frequency, it is critical to have a simple and accurate reliability model which estimates the value of fault rate considering supply voltage and operating frequency of a circuit. In this paper, we propose an accurate formula for analytic modeling of the soft error rate of a system which can be used to precisely track the reliability of the system under dynamic voltage and frequency adjustments. The experimental results of this paper prove that our proposed model offers precise estimates of reliability in accordance with the results of accurate soft error rate (SER) estimation algorithm for ISCAS85’s benchmark circuits.     

Accelerated assessment of fine-grain AVF in NoC using a Multi-Cell Upsets considered fault injection

With the increasing threat of soft errors induced bits upset, Network on Chip (NoC) as the communication infrastructure in many-core systems has been proven a reliability bottleneck in a fault tolerant parallel system. The often-used metric Architecture Vulnerability Factor (AVF), measures the architecture-level soft error impacts to compromise the design cost of fault tolerant schemes and reliability well. As a complementary of existing estimation methods about standard IP like processor and Cache, this work aims at an accelerated fault injection methodology for the fine-grain AVF assessment in NoC via two components: (1) modeling the complex fault patterns of both Multi-Cell Upsets (MCU) and Single Bit Upset (SBU) in the standard Fault Injection (FI) method; (2) accelerating the estimation via classifying and exploiting the fine-grain metrics according to different error impacts. The comprehensive simulation results using the diverse configures (e.g., varying fault model, benchmark, traffic load, network size and fault list size) also demonstrate that the proposed approach (i) shrinks the estimation inaccuracy due to MCU patterns 18.89% underestimation in no protection case and 88.92% overestimation under ECC (Error Correction Coding) protection on average; (ii) achieves about 5× speedup without estimation accuracy loss via phased pre-analysis based on fine-grain classification; (iii) verifies ECC a cost-effective mechanism to protect NoC router: soft errors reduced by about 50% over the no protection case, with only less than 2% area overhead.     

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements     

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).     

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.     

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.     

Efficient algorithms to accurately compute derating factors of digital circuits

Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single event transients by unified computation of all derating factors. The proposed algorithms, based on propagation of error probabilities and shape of erroneous waveforms, are scalable to very large circuits. The experimental results and comparisons with Statistical Fault Injections (SFIs) using Monte-Carlo simulations confirm the accuracy (only 2% difference) and speedup (5–6 orders of magnitudes) of the proposed technique.     

Switch-level soft error emulation for SET-induced pulses of variable strengths

Due to the increased complexity of modern digital circuits, the use of simulation-based soft error detection methods has become cumbersome and very time-consuming. FPGA-based emulation provides an attractive alternative, as it can not only provide faster speed, but also handle highly complex circuits. In this work, a novel FPGA-based soft error detection technique is proposed, which enables detection of soft errors resulting from voltage pulses of different magnitudes induced by single-event transients (SETs). The paper analyzes the effect of transient injection location on soft error rate (SER) and applies the idea of transient equivalence to minimize resource overhead as well as speed-up emulation process. Switch-level implementations of ISCAS’85 benchmarks are designed using gate-level structures and experimental results are reported. The results show that an application of transient equivalence results in an emulation speed-up of 2.875 and reduces the memory utilization by 65%. An average soft error rate (SER) of 0.7-0.8 was achieved using the proposed strength-based detection with drain as transient injection location, showing that voltage pulses of magnitude smaller than logic threshold can eventually result in soft errors. Furthermore, the presented emulation-based soft error detection technique achieved significant speed-up of the order of 10⁶ compared to a customized simulation-based method.     

Uncoded symbol error rate estimation: methods and analysis

In wireless communications systems, channel quality estimates are often used to provide a measure of the quality of service or to enable resource allocation techniques that improve system capacity and/or user quality. The uncoded bit or symbol error rate (SER) is specified as a channel quality metric in second and third generation cellular systems (e.g., general packet radio service (GPRS), enhanced general packet radio service (EGPRS), and universal mobile telecommunications system (UMTS). Nonetheless, techniques to estimate the uncoded SER are typically outside the scope of these wireless standards and are not specified. In this paper, we analyze the performance of a number of uncoded SER estimation techniques, including a novel technique in which we use the soft information of the received symbols to obtain a fast and accurate estimate of the uncoded SER. The technique we introduce has been found to outperform, in terms of accuracy and required estimation interval, conventional hard-decision based techniques that use test-patterns, or use a decode/re-encode/compare approach . Our technique also outperforms the brute-force technique, which is to send a known test-pattern, demodulate it at the receiver, and count the observed discrepancies.     

A mixed-level framework to estimate SER induced by SEMT in advanced technologies

As the complementary metal oxide semiconductor feature size shrinks further, single event multiple transients (SEMTs) become more serious. However, SEMTs have not yet been appropriately modelled through traditional soft error rate (SER) estimation methods. Therefore, this paper presents a mixed-level framework to estimate SER induced by SEMTs. The precision of the proposed framework is verified through HSPICE simulation. The results show that multiple pulses and convergence of SEMTs significantly affect SER estimation.     

Intelligent bounds on modeling uncertainty: applications to sliding mode control

Robust control techniques such as sliding mode control (SMC) require a dynamic model of the plant and bounds on modeling uncertainty to formulate control laws with guaranteed stability. Although techniques for modeling dynamic systems and estimating model parameters are well established, very few procedures exist for estimating uncertainty bounds. In the case of SMC design, a conservative global bound is usually chosen to ensure closed-loop stability over the entire operating space. The primary drawbacks of this conservative, "hard computing" approach are excessive control activity and reduced performance, particularly in regions of the operating space where the model is accurate. In this paper, a novel approach to estimating uncertainty bounds for dynamic systems is introduced. This "soft computing" approach uses a unique artificial neural network, the 2-Sigma network, to bound modeling uncertainty adaptively. This fusion of intelligent uncertainty bound estimation with traditional SMC results in a control algorithm that is both robust and adaptive. Simulations and experimental demonstrations conducted on a magnetic levitation system confirm these capabilities and reveal excellent tracking performance without excessive control activity.     

An efficient reliability estimation method for CNTFET-based logic circuits

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.     

Error propagation analysis of V-BLAST with channel-estimation errors

In this letter, expressions are given for the symbol-error rate (SER) of the Vertical Bell Laboratories Layered Space-Time (V-BLAST) system, taking into account error propagation due to channel-estimation errors. In addition to error propagation, suboptimal substream ordering due to imperfect channel estimates is accounted for. First, the conditional SER is determined using the distribution of the signal-to-interference-plus-noise ratio of each substream, conditioned on the channel estimate. Then, the average SER as a function of the channel estimation error-to-signal ratio (ESR) is upper bounded by averaging over the distribution of the channel estimates. The upper bound on the SER is tighter than previous bounds in the literature. Comparisons with exact simulations demonstrate the accuracy of the SER expressions for a large range of ESRs.     

Performance Analysis of Space-Time Block Codes with Transmit Antenna Selection in Nakagami-m Fading Channels

In this paper, multiple-input multiple-output systems employing space-time block codes (STBCs) with transmit antenna selection (TAS) are examined for flat Nakagami-m fading channels. Exact symbol error rate (SER) expressions for M-ary modulation techniques are derived by using the moment generating function based analysis method. In the SER analysis, the receiver is assumed to use maximal ratio combining whereas a subset of transmit antennas that maximizes the instantaneous received signal-to-noise ratio (SNR) is selected for STBC transmission. The analytical SER results are validated by Monte Carlo simulations. By deriving upper and lower bounds for SER expressions, it is shown that TAS/STBC schemes achieve full diversity orders at high SNRs.     

软硬件协同设计的SEU故障注入技术研究

针对现有容错计算机故障注入方法缺乏对空间环境中频发的单粒子故障模型的支持,本文提出了一种利用背板技术的软硬件协同仿真与故障注入技术,分别针对寄存器部件和存储器部件的特性,设计了多位错误的单粒子故障模型,在寄存器传输级实现了通过软件生成故障并注入到硬件设计中的软硬件协同故障注入方案,避免了在硬件设计中修改代码生成故障破坏系统完整性的问题.基于Leon2内核的故障注入实验表明,本文设计的平台为处理器容错设计提供了一个自动化、非侵入、低开销的故障注入和可靠性评估方案.