Electro-conductive adhesives for high density package and flip-chip interconnections

Dispensable isotropic conductive adhesives (ICA) and snap-curing anisotropic conductive adhesives (ACA) are developed through the EC funded Brite EuRam project DACTEL #BE95-1503. They show very promising capabilities for high-density applications when compared to benchmark electro-conductive adhesives.As first high-density application, assemblies of ceramic and plastic ball grid array/land grid array (LGA) on FR4 with DAC3-102/14 ICA are realized. Mixed assemblies solder/ICA show poor results, especially during aging. Full polymer LGA assemblies are built successfully. Daisy chains with hundreds of transitions component/substrate present resistances as low as 4 Ω. After comparison with benchmark products, CLGAs show themselves to be particularly reliable under moisture conditioning.Secondly, flip-chip assemblies on board, of medium sized chips bumped with electroless NiAu and using DAC2-143/02 ACA, are performed. Contact resistances as low as 10 mΩ are produced. For this application, reliability results are succinct.Finally, flip-chip assemblies on glass of slim chips with NiAu bump pitch down to 80 μm, by means of the newly developed DAC2-143/02 ACA, are demonstrated. The material shows better performances than a benchmark anisotropic conductive film, where measurements reveal contact resistances lower than the sheet resistance of the transparent indium tin oxide metallization used in display applications. Thermal cycling and temperature storage reveal good behavior of the ACA paste.     

高功率密度模块电源中采用的新材料和新技术

长期以来由于在通信设备电源设计中广泛采用分布供电方式,小功率模块电源(100W以下)一直占据着模块电源的主导地位,然而随着设备功能不断升级,局部集中供电方式因成本较低又被重新提起,在这种形势下,大功率(>100W)、高密度、高可靠性的模块电源正越来越多地得到广泛应用,和以往的体积笨重、性能一般的大功率模块电源相比,以半砖、全砖封装形式为代表的高功率密度模块电源,有以下几方面的特点:国际流行的工业标准封装,     

A novel approach to fabricate a PPy/p-type Si heterojunction

In this paper, we report an innovative method to generate a polypyrrole (PPy)/p-type Si junction. This method includes three fabrication steps. First, a PPy thin film is coated on a polymethylmethacrylate (PMMA) sheet. Second, a microstructure-formed p-type Si mold is inserted into the PMMA sheet. Finally, after separation of the mold and the substrate, the part of the PPy right underneath convex mold structures is removed from the PMMA sheet and attached to the convex mold structures, which form a PPy–Si junction. This junction has demonstrated diode-like characteristics. Compared with existing lithographic approaches, the developed method is simple and does not involve aggressive chemistry in patterning conducting polymers. Although this approach was employed here to particularly generate a PPy–Si junction, it can also be potentially applied to fabricate many other types of conducting polymer based devices, like light emitting diodes, light sensing arrays, transistors, and capacitors.     

VDNROM: A novel four-physical-bits/cell vertical channel dual-nitride-trapping-layers ROM for high density flash memory applications

A novel vertical channel dual-nitride-trapping-layer ROM (VDNROM) flash memory with oxide–nitride–oxide–nitride–oxide (ONONO) dielectrics stack is proposed and experimentally demonstrated. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the gate length scaling, and can have high capability of cell area shrinking. The fabrication process of this VDNROM device is basically compatible with planar CMOS technology. The VDNROM cell can be programmed and erased by the hot carrier injection to the localized trapping dual-nitride layers, so it can achieve a four-physical-bits storage capability each cell. The reliability behaviors including the cycling endurance and the bake retention at 150 °C have also been investigated and show the acceptable characteristics. The experiment results verify the VDNROM cell as a good candidate for high density applications.     

Development of three-dimensional memory die stack packages usingpolymer insulated sidewall technique

A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of: (1) wafer cutting into die segments; (2) die passivation including sidewall insulation; (3) via opening on the original I/O pads; (4) I/O redistribution from center pads to sidewall; (5) bare die stacking using polymer adhesive; (6) sidewall interconnection; and (7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces (1) better chip-to-wafer yields and (2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85°C/85% test     

Process compatible silicon-germanium-antimony heating layer for high density phase-change memory applications

The effects of SiGeSb heating layers, formed at room temperature by a sputtering method, on the performance of phase-change memory devices were investigated. The amount of Sb atoms in SiGeSb films was modified by changing sputtering power for a Sb target, and the resulting resistivities of the films ranged from 2.5 to 3.75 × 10⁷ mΩ cm depending on Sb concentration. The reset current and the set pulse width of a phase-change memory device decreased with decreasing Sb concentration due to an increase of the electrical and thermal resistances. The SiGeSb heating layer, like a SiGe heating layer grown at 650 °C by a chemical vapor deposition (CVD) technique, resulted in lower programming current and higher speed than a conventional TiN heating layer. The sputtered SiGeSb film appears superior to the CVD SiGe film for integration with a CMOS process because of its low formation temperature.     

Development of novel fibers for telecoms application

This paper reviews the current situations of optical fibers used for terrestrial and submarine transmission systems as well as up-to-date R&;D on these fibers. The current fibers include standard single mode fibers (SMFs), non-zero dispersion shifted fibers (NZ-DSFs), and dispersion managed lines (DMLs). Even though these fibers show quite high and matured properties, the internet traffic is continuously growing, and around 2015–2020, it is expected that the current transmission fibers would become inadequate. To prepare for the future ultra high-capacity transmission, there are three important R&;D directions for transmission fibers. (1) Reducing non-linearity by means of enlarging Aeff and/or reducing attenuation loss. It is very important in the case of transmission systems using new multi-level signal formats. (2) Expanding the transmission band more than the current C- and/or L-Band by utilizing new transmission fibers. For example, holey fibers (HFs), which have an endlessly single mode (ESM) property, are one of the interesting candidates of the new transmission fibers. (3) Using Space Division Multiplexing (SDM) by using multi-core fibers. The multi-core fiber literally multiples the core number within a fiber dimension, which enables multiple transmission capacity per one fiber. In addition to the developments of transmission fibers, component fibers have also been studied and developed. Examples of R&;D on these component fibers will be also discussed in the latter part of this paper.     

一种提高光折变多重存储密度的记录方法

提出了一种新的双面交替写入了光折变多重存储的记录方法。利用读出时折射率栅在记录晶体中移动的特点 ,把不同全息图的折射率栅置于晶体中纵向分离的位置 ,最大限度的利用了整个记录晶体的折射率动态范围 ,提高了光折变多重存储的实际存储密度。双面交替写入是把最先写入的折射率栅置于记录晶体的中心 ,最后写入的两折射率栅置于记录晶体前后表面附近 ,能够获得均匀的衍射效率     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

Benzocyclobutene (BCB) dielectrics for the fabrication of high density,thin film multichip modules

A new class of organic dielectrics, benzocyclobutenes, 1, are described and their application to the fabrication of thin film multichip modules is detailed. Key properties for3, a siloxy containing BCB derivative include low dielectric constant (2.7), low loss (0.008 at 1 MHz), low water absorption (0.25% after 24 h water boil) and high degree of planarization (>90% from one layer coverage). All other properties meet the requirements necessary for fabrication of thin film MCM structures.     

Amorphous Ta-nanocrystalline RuOx diffusion barrier for lower electrode of high density memory devices

The effects of the amount of RuO₂ added in the Ta film on the electrical properties of a Ta-RuO₂ diffusion barrier were investigated using n⁺⁺-poly-Si substrate at a temperature range of 650–800°C. For the Ta layer prepared without RuO₂ addition, Ta₂O₅ phase formed after annealing at 650°C by reaction between Ta and external oxygen, leading to a higher total resistance and a non-linear I-V curve. Meanwhile, in the case of the Ta film being deposited with RuO₂ incorporation, not only a lower total resistance and ohmic characteristics exhibited, but also the bottom electrode structure was retained up to 800°C, attributing to the formation of a conductive RuO₂ crystalline phase in the barrier film by reaction with the indiffused oxygen because of a Ta amorphous structure formed by chemially strong Ta-O or Ta-Ru-O bonds and a large amount of conductive RuO₂ added. Since a kinetic barrier for nucleation in formation of the crystalline Ta₂O₅ phase from an amorphous Ta(O) phase is much higher than that of crystalline RuO₂ phase from nanocrystalline RuO_x phase, the formation of the RuO₂ phase by reaction between the indiffused oxygen and the RuO_x nanocrystallites is kinetically more favorable than that of Ta₂O₅ phase.     

Development of a high density pixel multichip module at Fermilab

At Fermilab, both pixel detector multichip module and sensor hybridization are being developed for the BTeV experiment. The module is composed of three layers. The lowest layer is formed by the readout integrated circuits (ICs). The backs of the ICs are in thermal contact with the supporting structure, while the tops are flip-chip bump bonded to a pixel sensor. A low mass flex-circuit interconnect is glued on the top of this assembly, and the readout IC pads are wire-bonded to the circuit. The BTeV pixel detector is based on a design relying on this hybrid approach. This method offers maximum flexibility in the development process, choice of fabrication technologies, and the choice of sensor material. This paper presents strategies to handle the required data rate and performance characteristics of the pixel module prototypes     

Low-resistance polysilicon process in contact application for high density devices

For the lowest resistance, it is required to have the epitaxial silicon contact between the silicon plug and the substrate and good step coverage at the high aspect-ratio contact holes, simultaneously. In this work, a double polysilicon (DPS) deposition technique was proposed for the requirements. The first, thin silicon layer is deposited in a single-wafer process chamber with an in-situ H₂-RTP (rapid thermal process) treatment for the epitaxial contact, and the second silicon layer is formed in a batch-type furnace for good step coverage. From chain resistance, Kelvin R_c, and current-voltage (I–V) measurement, the DPS process meets both low resistance and good uniformity, so that it suggests a breakthrough in the small-sized, semiconductor device application.     

一种SOI高温压力传感器

SOI高温压力传感器是一种新型的高性能,高品质的压力传感器。本文提出了一种SOI高温压力传感器的结构,并从掺杂浓度和功率等关键因素进行了高温分析。设计了敏感芯片 的工艺流程以及关键工艺参数。通过在室温和高温下的测量,结果表明非线性误差小于0.1%,迟滞性小于0.5%,敏感芯片可以在350℃高温下工作。本文为高温压力传感器的研究提供了参考。     

高密度储能脉冲电容器的研制

我国第一台高功率激光装置能源系统中使用的脉冲电容器于1982年研制成功,并通过鉴定,其储能密度为0.145J/cm~3,在纯纸介质的脉冲电容器同类产品中居领先地位。随着高功率激光装置的不断发展,它的功率等级在不断扩大和升级。因此对能源系统的要求不断提高,要求能源占地少,储能大,所以必须使电容器储能密度进一步提高。 从脉冲电容器储能密度公式     

High electromagnetic shielding of plastic package for 2.5-Gb/s optical transceiver modules

A lightweight, low-cost plastic package for a 2.5-Gb/s optical transceiver module, that also has good electromagnetic shielding properties, has been fabricated using woven continuous carbon fiber (CCF) epoxy composite. The shielding effectiveness (SE) of the CCF epoxy composite has been modeled theoretically and measured from 500 MHz to 3 GHz using the ASTM D4935 and a near-field test method. Two types of weaving patterns were studied: a balanced twill structure (BTS) and a parallel structure. The BTS was able to achieve an SE of about 80 dB under plane wave conditions and about 50 dB under near-field conditions because of the numerous conductive between crossing fibers. The SE of the proposed package is at least 20 dB greater than the previous package which used a liquid crystal polymer composite. In addition to better shielding performance, the proposed package costs less because it uses less carbon fiber. The proposed package for an optical transceiver is suitable for use in a low-cost lightwave transmission system     

Interfacial fracture toughness for delamination growth predictionin a novel peripheral array package

The objective of this study is to predict interfacial delamination propagation that may inhibit the performance of a novel surface mountable, high input/output (I/O) electronic package. Incorporation of such predictions in the design phase of the package can lead to judicial selection of materials and geometric parameters such that the interfacial delamination based failures can be avoided. This, in turn, leads to significant cost savings and shorter time-to-market due to the shortening of the prototyping and qualification testing phases. The focus of the present study is the prediction of potential delaminations at the encapsulant-backplate interface in a very small peripheral array (VSPA) package during manufacturing. The delamination growth prediction is based on the comparison of interfacial fracture parameters obtained from the numerical simulations to appropriate critical values determined experimentally using controlled fracture toughness tests. In this paper, the fracture toughness of the encapsulant/backplate interface is characterized using a fracture toughness test that requires simple test specimen, fixture and loading geometries. The critical interfacial fracture toughness and the fracture mode mixity are determined using closed-form and finite element analyses of the test specimen geometries, taking into consideration the effects of thermo-mechanical residual stresses resulting from the test specimen fabrication process. Furthermore, an experimental characterization of the encapsulant material is also conducted in order to assess the effects of its time- and temperature-dependent thermomechanical response on the fracture toughness of the encapsulant-backplate interface     

Platinum chemical mechanical polishing (CMP) characteristics for high density ferroelectric memory applications

The key component of ferroelectric random access memory (FeRAM) is a capacitor including a ferroelectric thin film and electrode materials. Platinum is one of the suitable metals which meet requirements such as low resistivity, high thermal stability, and good oxygen resistance. Generally, the ferroelectric and the electrode materials were patterned by a plasma etching process. The application possibility of chemical mechanical polishing (CMP) processes to the patterning of ferroelectric thin film instead of plasma etching was investigated in our previous study for improvement of an angled sidewall which prevents the densification of FeRAM. In this study, the characteristics of platinum CMP for FeRAM applications were also investigated by an approach as bottom electrode materials of ferroelectric material in CMP patterning. The removal rate was increased from 24.81 nm/min by the only alumina slurry (0.0 wt% of H₂O₂ oxidizer) to 113.59 nm/min at 10.0 wt% of H₂O₂ oxidizer. Electrochemical study of platinum and alumina slurry with various concentrations of H₂O₂ was performed in order to investigate the change of the removal rate. The decreased particle size in the alumina slurry with an addition of 10.0 wt% H₂O₂ oxidizer made the improved surface roughness of the platinum thin films. Micro-scratches were observed in all polished samples.     

Development of a novel image sensor and its application to analysis of automobile components

The authors have developed a novel image sensor for continuous conditioned monitoring of high-precision tolerances of a complex automotive product. A novel mechanooptical arrangement has been designed and validated to capture the images/silhouettes of the components as input into a neural network designed on approximate reasoning architecture. The design is extensible to handle a large number of rules, and the speed of inference is almost independent of the number of rules.