Investigation of the degradation of smooth SiGe epitaxial layer on Si substrate

The degradation of smooth SiGe epitaxial layer was investigated by transmission electron microscopy (TEM), X-ray reflectivity (XRR) and atomic force microscopy (AFM). It was shown from AFM results that the crosshatch was formed with increasing annealing temperature, which indicated the degradation of smooth surface. The surface degradation was caused by the internal dislocations, which were observed by plan-view TEM (PTEM) and cross-sectional TEM (XTEM). From XTEM, the sharp interface between SiGe top layer and Si substrate was broadened and there were a lot of 60° dislocations formed in SiGe top layer, which resulted in the crosshatch on the surface. The crosshatch was also verified by PTEM.     

Berkovich nanoindentation on single SiGe epitaxial films

In this work, a Berkovich nanoindentation was employed to measure the elastic–plastic transition of the SiGe film. Pop-in events are observed from the penetration depths of 17.1 to 18.2 nm, 15.2 to 15.65 nm, and 15.5 to 17 nm; while the conditions at RT are annealed at 800 and 900 °C, respectively. However, pop-in events are not clear at the condition of 1000 °C because of the highest thermal activation. To explain the experiments, final depth after complete unloading (h_f), maximum indentation depth (h_max) and recovery ratio (h_f/h_max) data are given in the range of 0.215, 0.257, and 0.447 when the conditions are at 800, 900, and 1000 °C, respectively. We can refereed that the conclusion of a smaller indenter radius might result in elbows. Thermal activation is used to assist in the formation of islands on the surface and leads to the increased Rms. Transmission electron microscopy results revealed a serial nucleation seed that induced dislocation propagation after 900 °C-annealing, and creating a number of random dislocations after 1000 °C-annealing. The importance of the relative elastic–plastic transition of 503 nm SiGe films and pop-in (the load penetration curves exhibits one or more discontinuities on loading which is called as pop-in event) and elbow (a longer portion of the unloading curve) events on the response of the thermal treatment is highlighted.     

Fabrication and current-drive of SiGe/Si 'Micro-origami' epitaxial MEMS device on SOI substrate

A micromirror structure with SiGe/Si heteroepitaxial layer on a silicon-on-insulator (SOI) substrate using a 'Micro-origami' technique has been successfully fabricated. The micromirror is supported by two curved hinge structures. The device is driven by application of a current, and net angular displacements larger than 10/spl deg/ (static) and 30/spl deg/ (in resonance) were obtained. These values are comparable with or even larger than the reported values for other MEMS optical switches or beam scanning devices. The experimental results suggest that the movement is evoked by a thermal effect. The Micro-origami device has advantages of low operation voltage smaller than 2 V, and structural compatibility with the Si or SiGe LSIs.     

A selective epitaxial SiGe/Si planar photodetector for Si-basedOEIC's

A P-i-N SiGe/Si superlattice photodetector with a planar structure has been developed for Si-based opto-electronic integrated circuits. To make the planar structure, a novel SiGe/Si selective epitaxial growth technology which uses cold wall ultrahigh-vacuum/chemical vapor deposition has been newly developed. The P-i-N planar SiGe/Si photodetector has an undoped 30-Å Si_0.9Ge_0.1/320-Å Si, 30 periods, superlattice absorption layer, a 0.1-μm P-Si buffer layer, and a 0.2-μm P⁺-Si contact layer on a bonded silicon-on-insulator (η_ext). The bonded SOI is used to increase the external quantum efficiency (η_ext) of the photodetector. Moreover, a 63-μm deep/128-μm wide trench, to achieve simple and stable coupling of an optical fiber to the photodetector, is formed in the silicon chip. The P-i-N planar photodetector exhibits a high η_ext of 25-29% with a low dark current of 0.5 pA/μm² and a high-frequency photo response of 10.5 GHz at λ=0.98 μm     

Investigation of the implanted phosphorus in a boron doped SiGe epitaxial layer

Phosphorus diffusion into strained SiGe layers was studied by different methods. Doping profiles and carrier concentration profiles N(x), depth of pn junction, Ge content in SiGe and thickness of epitaxial layer were measured and simulated. Several experimental methods such as secondary ion mass spectroscopy, spreading resistance method, Raman spectroscopy—and process simulator ISE TCAD have been used. The results obtained by different methods and at different places of work have been compared and analysed.     

Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolartransistors

In this work a comprehensive investigation of low-frequency noise in ultrahigh vacuum/chemical vapor deposition (UHV/CVD) Si and SiGe bipolar transistors is presented. The magnitude of the noise of SiGe transistors is found to be comparable to the Si devices for the identical profile, geometry, and bias. A comparison with different technologies demonstrates that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs heterojunction bipolar transistors (HBT's) and conventional Si bipolar junction transistors (BJT's). Results from different bias configurations show that the 1/f base noise source is dominant in these devices. The combination of a 1/Area dependence on geometry and near quadratic dependence on base current indicates that the 1/f noise sources are homogeneously distributed over the entire emitter area and are probably located at the polysilicon-Si interface. Generation/recombination (Gm) noise and random telegraph signal (RTS) noise was observed in selected Si and SiGe devices. The bias dependence and temperature measurements suggest that these G/R centers are located in the base-emitter space charge region. The activation energies of the G/R traps participating in these noise processes were found to be within 250 meV of the conduction and valence band edges     

Si-gate CMOS devices on a Si lateral solid-phase epitaxial layer

Si-gate CMOS devices fabricated on a lateral solid-phase epitaxial Si layer grown from vacuum-deposited amorphous Si over SiO₂ patterns are discussed. Electrical characteristics are examined and correlated with microstructural characteristics of the layer by performing transmission electron microscopy on actual transistors. The layer can be divided into three regions. Carrier mobilities obtained from each region are discussed in terms of the crystalline quality. The maximum obtained field-effect mobilities are 570 cm²/V-s and 160 cm²/V-s for n-channel and p-channel transistors, respectively. The SMOS inverter chain with 100 stages and a channel length of 1.5 μm has a delay time of 310 ps per gate. These results indicate that the lateral solid-phase epitaxy has potential for the fabrication of high-speed silicon-on-insulator devices     

Si衬底GaN基多量子阱外延材料的TEM研究

本文采用高分辨透射电子显微技术对在Si衬底生长的GaN基多量子阱外延材料的位错特征、外延层与衬底的晶体取向关系及界面的结晶形态等微观结构进行了分析和研究.结果表明:Si衬底生长的GaN与衬底有一定的取向关系;材料在MQW附近的穿透位错密度达108 cm-2量级,且多数为刃型位错;样品A的多量子阱下方可见平行于界面方向的...     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.     

Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers

We report an interdigitated p-i-n photodetector fabricated on a 1-/spl mu/m-thick Ge epitaxial layer grown on a Si substrate using a 10-/spl mu/m-thick graded SiGe buffer layer. A growth rate of 45 /spl Aring//s/spl sim/60 /spl Aring//s was achieved using low-energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had a threading dislocation density of 10/sup 5/ cm/sup -2/ and a rms surface roughness of 3.28 nm. The 3-dB bandwidth and the external quantum efficiency were measured on a photodetector having 1-/spl mu/m finger width and 2-/spl mu/m spacing with a 25/spl times/28 /spl mu/m/sup 2/ active area. At a wavelength of 1.3 /spl mu/m, the bandwidth was 2.2, 3.5, and 3.8 GHz at bias voltages of -1, -3, and -5 V, respectively. The dark current was 3.2 and 5.0 /spl mu/A at -3 and -5 V, respectively. This photodetector exhibited an external quantum efficiency of 49% at a wavelength of 1.3 /spl mu/m.     

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).     

采用低温缓冲层技术在Si衬底上生长高质量Ge薄膜

采用低温缓冲层技术,在Si衬底上生长了质量优良的Ge薄膜。利用原子力显微镜（AFM）、双晶X射线衍射（XRD）和拉曼散射等研究了薄膜的晶体质量。结果表明,由于无法抑制三维岛状生长,低温Ge缓冲层的表面是起伏的。然而,Ge与Si间的压应变几乎完全弛豫。当缓冲层足够厚时,后续高温Ge外延层的生长能够使粗糙的表面变得平整。在...     

Compositional inhomogeneity at the epitaxial layer and substrate interface of AlGaAs/GaAs heterostructures

Carrier concentration spikes at the epilayer/substrate interface were observed in some two-dimensional electron gas AIGaAs/GaAs structures grown by low pressure organometallic vapor phase epitaxy. Using secondary ion mass spectroscopy, the carrier spikes were correlated with indium. Under certain growth conditions an anomalous interfacial layer, which is compositionally inhomogeneous, is formed producing an enhanced carrier density. Procedures are described which reduce the presence of indium at the epilayer/substrate interface and eliminate the carrier spike.     

射频Si/SiGe/Si HBT的研究

在Si／SiGe／SiHBT与Si工艺兼容的研究基础上，对射频Si／SiGe／SiHBT的射频特性和制备工艺进行了研究，分析了与器件结构有关的关键参数寄生电容和寄生电阻与Si／SiGe/Si HBT的特征频率fT和最高振荡频率fmax的关系，成功地制备了fT为2．5CHz、fmax为2．3GHz的射频Si／SiGe／SiHBT，为具有更好的射频性能的Si／SiGe／Si HBT的研究建立了基础。     

Evaluation of crystallinity of GaN epitaxial layer after wafer dicing

The crystallinity of GaN epitaxial layers on sapphire substrates following laser dicing was evaluated by Raman spectroscopy. Dicing was carried out using either full laser ablation or laser scribing followed by breaking. The results indicated that in a region within about 40 μm from the edges of the diced chips, the Raman peaks were shifted to lower wavenumber than near the chip center. The shifted peaks were at positions intermediate between those for the GaN epitaxial layer before dicing and those for a bulk GaN crystal. These results indicate that stress relaxation occurred near the edges of the diced chips.     

Effect of tensile-strained Si layer on photoluminescence of Ge(Si) self-assembled islands grown on relaxed SiGe/Si(001) buffer layers

The results of studying the photoluminescence of the structures with Ge(Si) self-assembled islands embedded into tensile-strained Si layer are reported. The structures were grown on smooth relaxed Si_{1 ? x} Ge_x/Si(001) (x = 0.2–0.3) buffer layers. The photoluminescence peak found in the photoluminescence spectra of the studied structures is related to the indirect (in real space) optical transition between the holes localized in the Ge(Si) islands and electrons localized in the tensile-strained Si layers under and above an island. It is shown that one can efficiently control the position of the photoluminescence peak for a specified type of structure by varying the thickness of the strained Si layers. It is found that, at 77 K, the intensity of the photoluminescence signal from the heterostructures with Ge(Si) self-assembled islands contained between the tensile-strained Si layers exceeds by an order of magnitude the intensity of the photoluminescence signal from the GeSi structures with islands formed on the Si(001) substrates.     

Evaluation of the influence of an embedded porous silicon layer on the bulk lifetime of epitaxial layers and the interface recombination at the epitaxial layer/porous silicon interface

Porous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (10¹⁶/cm³) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p⁺ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p⁺ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p⁺ substrate interface (S ≅ 10³ cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.     

Si(001)外延ZnSe薄膜界面原子的结合与成键

基于密度泛函理论的第一性原理计算,通过对Si(001)和氮化Si(001)表面单层Zn/Se原子结合的方式,模拟ZnSe外延薄膜的二维生长模式,从单层原子结合能、界面原子电子得失、共价结合成键的角度解释了Zn/Se原子在衬底表面的黏附性问题,阐述了薄膜生长初期界面无定形Se出现等现象,分析了氮化Si(001)表面对薄膜二维均匀生长的作用,结果显示N的引入缓和了Si衬底的非极性共价结合与ZnSe原子间的极性离子键结合之间的异质差异。     

Studies on the growth of CdTe on Si using ge interfacial layer in an organometallic vapor phase epitaxial system

Epitaxial CdTe layers were grown using organometallic vapor phase epitaxy on Si substrates with a Ge buffer layer. Ge layer was grown in the same reactor using germane gas and the reaction of germane gas with the native Si surface is studied in detail at low temperature. It is shown that germane gas can be used to “clean” the Si surface oxide prior to CdTe growth by first reducing the thin native oxide that may be present on Si. When Ge layer was grown on Si using germane gas, an induction period was observed before the continuous layer of Ge growth starts. This induction period is a function of the thickness of the native oxide present on Si and possible reasons for this behavior are outlined. Secondary ion mass spectrometry (SIMS) data show negligible outdiffusion and cross contamination of Ge in CdTe.