The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

An optimization study of underfill dispensing volume

The underfill dispensing volume has been modeled and verified through both experiments and application of statistical technique. The model established is capable of estimating the operating range of the dispensing volume of a defined flip chip assembly and is targeted to reduce wastage as well whilst fulfilling the reliability requirement. The model has taken into consideration the reliability factor, e.g., presence of fillet; manufacturing tolerance of bumps size and standoff variation. In this study, the actual volume for flip chip assemblies prepared in a controlled manner, so that fillets were seen on all sides, was compared with the recommended underfill volume. It was found that the model tended to yield a higher volume and it is concluded that this variation is related to the over estimation of the fillet element in the formulation. For reliability assessment, these flip chip assemblies were examined under C-mode SAM and no voids were found. These flip chip assemblies also passed electrical testing after 500 cycles of air to air thermal cycles and therefore are proven to meet the reliability requirement.     

Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or "no-flow" flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.     

Effect of thermocapillary action in the underfill encapsulation of multi-stack ball grid array

Recent trend in electronic industries are demanding smaller chip packaging process along with increase in performance and reliability of the package. The introduction of Multi-stack Ball Grid Array (BGA) to enhance the performance of the conventional BGA flip chip has frequently encountered several hitches such as extended filling time and incomplete filling at the upper layer of the multi-stacks BGA. It has been found that the encapsulant lacks energy to flow at the upper layer due to lower hydrostatics pressure. In this paper, a straightforward solution by incorporating additional thermal energy in the encapsulant to increases its flow ability is introduced. This additional thermal energy at the upper layer produces a distinct temperature difference between the upper and lower layers, or simply thermal delta. This research attempts to demonstrate the effectiveness of thermal delta in solving the aforementioned flow problem during encapsulation process of multi-stacks BGA, by means of experiment and numerical simulation. The findings have shown that the experimental data compares well with the simulation results. It was also found that the implementation of thermal delta substantially reduces the filling time across the multi-stack packages. This study reveals the potential of thermocapillary-driven underfill encapsulation being widely adopted in future industrial encapsulation of multi-stacks BGA packaging.     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

FCOB器件在热循环载荷下的界面层裂研究

界面层裂是塑封半导体器件的主要失效模式之一。采用通用有限元软件MSC.MARC,研究了FCOB(基板倒装焊)器件在热循环(–55~+125℃)载荷作用下,底充胶与芯片界面的层裂问题。结果表明:底充胶与芯片界面最易出现分层,分层扩展的位置都在该界面的边缘拐角处;如果分层导致底充胶开裂,开裂的方向大约是35°。     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Anisotropic behavior of the capillary action in flip chip underfill

An underfill encapsulant can be used to improve the long-term reliability of flip chip interconnecting system by filling the gap between the chip and substrate around the solder bumps. The underfill encapsulant was filled by a capillary flow. This study was devoted to investigate the anisotropic effects of the capillary action induced by the solder bumps. A modified Hele-Shaw flow model, considering the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. A capillary force model, depending on the direction of filling flow, for full array solder bumps was proposed. The capillary force was formulated based on quadrilateral arrangement of solder bumps. It was found that the capillary action is not the same for different directions. In the 45° direction, enhancement of the capillary flow was noticed for a bump pitch within a critical value. The edge preferential flow during the underfill experiment could be attributed to the anisotropic behavior of the capillary action.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill,novel terminal pad structures,and processing optimization

Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K<3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.     

Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

FC传递成型封装的可行性分析

对于FC封装来说,一次成型的生产效率具有无可比拟的优势,而且固态塑封料相对于液态塑封料在性能上也具有很明显的优点,因此塑封料的制造商一直都在研究一次成型的FC用封装材料。本篇文章主要就目前所使用液态灌封材料和固态塑封料之间的性能进行比较,并就目前传统的封装工艺及其他专用材料、封装设备如何改进才能够适应FC封装进行简单的分析。     

Adhesion and toughening mechanisms at underfill interfaces forflip-chip-on-organic-substrate packaging

The flip chip-on-organic-substrate packaging technology utilizes a particulate reinforced epoxy as the underfill (UF) to adhere the chip to the package or board, Although the use of underfill encapsulation leads to improved reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major concern for assembly yield loss and package reliability. In spite of their importance, the adhesion and fracture behaviors of the underfill interfaces have not been investigated until recently. Considerable controversy exists over the effects of underfill formulation and the adhesion and toughening mechanisms of the interfaces. The present work focuses on investigating the effects of several key variables on the interface adhesion strengths for UF/chip and UF/organic substrate systems. These variables are underfill organosilane content, filler particle content, rubber particle content, surface morphology and chemistry of the chip and organic substrates. The approach of this study is to measure the effect of these variables on the interfacial fracture energy using the double-cantilever-beam (DCB) techniques. The results demonstrate that the underfill interfacial adhesion and fracture characteristics are controlled by several distinct but competing mechanisms, such as formation of primary bonds, crack-pinning by glass fillers, debonding of glass filler from epoxy matrix (defect formation), and cavitation and shearing induced by rubber particles. Fundamental understanding of the interfacial adhesion and toughening mechanisms can provide guidance for developing new processes and materials to enhance interfacial adhesion and reliability     

Dynamic flow measurements of capillary underfill through a bump array in flip chip package

This study investigated the dynamic variations of flow and meniscus during underfill process using flow visualization techniques to understand physics of capillary flows. For the quantitative flow visualization, a high speed micro particle image velocimetry (μPIV) was applied to a transparent flip chip specimen with arrayed bump structure. As an underfill liquid, glycerin was filled into the flip chip specimen by capillary action. The present visualization technique offers time-varying movement of meniscus and phase-locked velocity fields frozen to the meniscus position. To observe the dynamic contact angle between parallel plates, an in situ measurement technique was developed in the present study. Then, the filling time was compared with analytical models. From this experiment, it was found that the meniscus velocity and the contact angle vary in-phase according to the position of meniscus. The phase-locked velocity fields show velocity gradients on the meniscus surface which gives rise to the breakdown of equilibrium contact angle. Consequently, the detailed filling time has different behavior from the analytical models.     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies     

倒装芯片底部填充工艺

从热疲劳故障的角度论述了倒装芯片底部填充的必要性，介绍了倒装芯片底部填充的参数控制。通过正确的底部填充，可提高倒装芯片组装的成品率和可靠性。     

倒装焊后清洗工艺及其对底部填充的影响

倒装焊封装是通过将整个芯片有源面进行管脚阵列排布并预制焊料凸点,通过倒装焊工艺进行互连,与传统引线键合技术相比具有更高的组装密度及信号传输速率,是实现电子产品小型化、轻量化、多功能化的关键技术之一.对于小尺寸微节距的倒装焊芯片来说,焊后清洗的难度相对更大,因此清洗技术也是影响倒装焊工艺的重要因素.针对不同清洗方式及参数...