An all-analog multiphase delay-locked loop using a replica delayline for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm²) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7]     

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 ${hbox{mm}}^{2}$ active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.      

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm²) and dissipates less power (15 mW) than other wide-range DLLs.     

FPGA芯片内数字时钟管理器的设计与实现

在FPGA芯片内,数字时钟管理器(DCM)不可或缺,DCM主要完成去时钟偏移、频率综合和相位调整的功能,其分别由延迟锁相环(DLL)、数字频率合成器(DFS)以及数字相移器(DPS)三个模块来实现。对这三个模块的原理及设计进行了详细地阐述,并给出了仿真结果,该DCM电路通过了0.13μm工艺流片。测试结果表明,在低频模式下,该DCM能工作在24～230 MHz之间;在高频模式下,该DCM能工作在48～450 MHz之间,其输入及输出抖动容忍度在低频模式下能达到300 ps,在高频模式下能达到150 ps。     

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.     

A new DLL-based approach for all-digital multiphase clock generation

A new DLL-based approach for all-digital multiphase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital communication applications.     

A 1-V 4-GHz wide tuning range voltage-controlled ring oscillator in 0.18 μm CMOS

A new differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for low voltage and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control can get rid of the restriction that control voltage is unable to cover the full range of power supply voltage in a conventional VCRO. A three-stage VCRO chip working with 1 V power supply voltage is constructed using 0.18 μm 1P6M CMOS process for verifying the efficacy of the proposed differential delay cell. Measured results of the VCRO chip show that a wide range of operation frequency from 4.09 GHz to 479 MHz, a tuning range of 88%, is achieved for the full range of control voltage from 0 to 1 V. The power consumptions of the chip are 13 and 4 mW for oscillation outputs of 4.09 GHz and 479 MHz, respectively. The measured phase noise is −93.3 dBc/Hz at 1 MHz offset from 4.09 GHz center frequency. The core area of the chip is 106 μm×76.2 μm.     

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode

This paper presents a low-power digital DLL-based clock generator. Once the DLL is locked, it operates in open-loop mode to reduce deterministic clock jitter and the power dissipation caused by DLL dithering. To keep track of any potential phase error introduced by environmental variations, a compensation mechanism is employed. In addition, a robust DLL-based frequency multiplication technique is proposed. The DLL-based clock generator is designed and fabricated in a 90 nm CMOS process in two different versions. Utilizing the proposed technique, the output jitter caused by DLL dithering is reduced significantly. Furthermore, the measured total power savings in the open-loop mode in comparison with the conventional closed-loop operation is about 14%.      

A new ADPLL architecture dedicated to program clock references synchronization

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.     

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer andtemperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0°C to 85°C. The circuits were fabricated on a generic 0.5-μm digital CMOS process     

A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock

This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is adopted to generate multi-phase clocks. We propose a simple scheme for a frequency detector (FD) to overcome the limited frequency range and false lock problem of a conventional delay-locked loop (DLL) to reduce the complexity. In addition, a duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatches between rising and falling time of delay cells in the VCDL. Also, the proposed simple DLL architecture comprised of frequency and phase detectors has better process-portability. The proposed CDR is implemented in 0.18 μm technology and the active die area is 660 × 250 μm. The implemented DLL covers a frequency range from 62 to 128 MHz, which is limited only by the characteristics of the delay cell. The peak-to-peak jitter is less than 13 ps when the input frequency is 128 MHz, and the power consumption of the CDR except the input buffer, equalizer, and de-serializer is 5.94 mW from the supply voltage of 1.8 V.     

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-/spl mu/m CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively.     

A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

This paper describes a delay-locked loop (DLL) circuit having two advancements, a dual-loop operation for a wide lock range and programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual-loop operation uses information from the initial time difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock range of the DLL to the lower frequency. In addition, incorporation of the programmable replica delay using antifuse circuitry and the internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on-chip and off-chip variations after the package process. The proposed DLL, fabricated on 0.16-μm DRAM process, operates over the wide range of 42-400 MHz with 2.3-V power supply. The measured results show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consuming 52 mW at 400 MHz     

A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiverwith dead-zone phase detection for robust clock/data recovery

For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3 × oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and intersymbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25-μm CMOS technology, operates at 2.5 GBaud over a 10-m 150-Ω STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10^-13     

A 250-MHz-2-GHz wide-range delay-locked loop

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.     

Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%. Moreover, it enhances the input clock signal driving ability and keeps the same duty cycle as input clock within range from 20% to 80% with a maximum duty error of 0.5%. The proposed circuit operation frequency range is from 100 MHz to 1 GHz. The proposed circuit has been fabricated in a 0.18 μm CMOS technology.