Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics

N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37 nm has been demonstrated with La₂O₃ as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37 nm in EOT. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

ZrO₂ thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N′-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H₂O as an oxidizing agent. Tetrakis (ethylmethylamino) zirconium (TEMA-Zr) was also evaluated for a comparative study. Physical properties of ALD-derived ZrO₂ thin films were studied using ellipsometry, grazing incidence XRD (GI-XRD), high resolution TEM (HRTEM), and atomic force microscopy (AFM). The ZrO₂ deposited using Zr-AMD showed a better thermal stability at high substrate temperature (>300 °C) compared to that using TEMA-Zr. GI-XRD analysis reveals that after 700 °C anneal both ZrO₂ films enter tetragonal phase. The electrical properties of N₂-annealed ZrO₂ film using Zr-AMD exhibit an EOT of 1.2 nm with leakage current density as low as 2 × 10⁻³ A/cm² (@V_fb−1 V). The new Zr amidinate is a promising ALD precursor for high-k dielectric applications.     

Improved property in organic light-emitting diode utilizing two Al/Alq3 layers

We reported on the fabrication of organic light-emitting devices (OLEDs) utilizing the two Al/Alq₃ layers and two electrodes. This novel green device with structure of Al(110 nm)/tris(8-hydroxyquinoline) aluminum (Alq₃)(65 nm)/Al(110 nm)/Alq₃(50 nm)/N,N′-dipheny1-N, N′-bis-(3-methy1phyeny1)-1, 1′-bipheny1-4, 4′-diamine (TPD)(60 nm)/ITO(60 nm)/Glass. TPD were used as holes transporting layer (HTL), and Alq₃ was used as electron transporting layer (ETL), at the same time, Alq₃ was also used as emitting layer (EL), Al and ITO were used as cathode and anode, respectively. The results showed that the device containing the two Al/Alq₃ layers and two electrodes had a higher brightness and electroluminescent efficiency than the device without this layer. At current density of 14 mA/cm², the brightness of the device with the two Al/Alq₃ layers reach 3693 cd/m², which is higher than the 2537 cd/m² of the Al/Alq₃/TPD:Alq₃/ITO/Glass device and the 1504.0 cd/m² of the Al/Alq₃/TPD/ITO/Glass. Turn-on voltage of the device with two Al/Alq₃ layers was 7 V, which is lower than the others.     

Properties of ALD HfTaxOy high-k layers deposited on chemical silicon oxide

HfTa_xO_y high-k dielectric layers with different compositions were deposited using ALD on 1 nm SiO₂ generated by ozone based cleaning of 200 mm Si(1 0 0) surface. Physical characterization of blanket layers and C-V mapping demonstrates that the ALD layers have excellent uniformity and controllable compositions. The layers with a composition of HfTaO_5.5 remain amorphous after annealing at 900 °C. The C-V measurements of MOS capacitors show no hysteresis, negligible frequency dispersion and interfacial state density smaller than 3 × 10¹¹ (cm⁻² eV⁻¹). k-value of the amorphous layers varies in the range from 20 to 25, depending on layer composition. The flat band voltage does not shift with the increase of EOT, implying that the effect of fixed charge densities in the layers is negligible. The I-V measurements show a leakage reduction comparable to that of the ALD HfO₂ layers.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Materials and interfaces issues in pentacene/PTCDI-C8 ambipolar organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for pentacene/N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C₈) ambipolar organic field-effect transistors (OFETs) in air ambient and in vacuum. An aqueous solution process was used to form the gelatin gate dielectric film on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. Pentacene morphology and interface roughness are two major factors affecting the electron and hole field-effect mobility (μ_FE) values of pentacene/PTCDI-C₈ ambipolar OFETs in vacuum and in air ambient. In contrast, water absorption in gelatin has higher contribution to the electron and hole μ_FE values in air ambient. The ambipolar performance of pentacene/PTCDI-C₈ ambipolar OFETs depends on their layer sequence. For example, when PTCDI-C₈ is deposited onto pentacene, i.e. in the structure of PTCDI-C₈/pentacene, unbalanced ambipolar characteristics appear. In contrast, better ambipolar performance occurs in the structure of pentacene/PTCDI-C₈. The optimum ambipolar characteristics with electron μ_FE of 0.85 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.95 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (40 nm)/PTCDI-C₈ (40 nm). Surprisingly, water absorption plays a crucial role in ambipolar performance. The device performance changes tremendously in pentacene/PTCDI-C₈ ambipolar OFETs due to the removal of water out of gelatin in vacuum. The optimum ambipolar characteristics with electron μ_FE of 0.008 cm² V⁻¹ s⁻¹ and hole μ_FE of 0.007 cm² V⁻¹ s⁻¹ occurs at the condition of pentacene (65 nm)/PTCDI-C₈ (40 nm). The roles of layer sequence, relative layer thickness, and water absorption are proposed to explain the ambipolar performance.     

Selection of rare earth silicates for highly scaled gate dielectrics

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La₂O₃ gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10¹¹ cmv⁻²/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51 nm has been successfully fabricated with a La₂O₃ gate dielectric on a Ce-silicate interfacial layer after annealing at 500 °C. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.     

Etching characteristics and plasma-induced damage of Ba0.65Sr0.35TiO3 thin films etched in CF4/Ar/O2 plasma

Sol-gel-derived Ba_0.65Sr_0.35TiO₃ (BST) thin films were etched in CF₄/Ar/O₂ plasma using magnetically enhanced reactive ion etching technology. The maximum etch rate of BST film is 8.47 nm/min when CF₄/Ar/O₂ gas mixing ratio is equal to 9/36/5. X-ray photoelectron spectroscopy analysis indicates the accumulation of fluorine-containing by-products on the etched surface due to their poor volatility, resulting in (Ba,Sr)-rich and (Ti,O)-deficient etched surface. Compared to the unetched counterparts, the etched Ba 3d_5/2, Ba 3d_3/2, Sr 3d_5/2, Sr 3d_3/2, Ti 2p_3/2, Ti 2p_1/2 and O 1s photoelectron peaks shift towards higher binding energy regions by amounts of 1.31, 1.30, 0.60, 0.79, 0.09, 0.46 and 0.50 eV, respectively. X-ray diffraction (XRD) analysis reveals that intensities of the etched BST (1 0 0), (1 1 0), (2 0 0) and (2 1 1) peaks are lowered and broadened. Raman spectra confirm that the Raman peaks of the etched film shift towards lower wave number regions with the values of 7, 6, 4 and 4 cm⁻¹, and the corresponding phonon lifetimes are longer than those of the unetched film because of the plasma-induced damage. When the etched films are postannealed at 650 °C for 20 min under an O₂ ambience, the chemical shifts of Ba 3d, Sr 3d, Ti 2p and O 1s peaks, the variations for atomic concentrations of Ba, Sr, Ti and O, and the Raman redshifts are reduced, while the corresponding XRD peak intensities increase. It is conceivable that the plasma-induced damage of the etched film could be partially recovered during the postannealing process.     

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9-50) and investigate its effects on conventional, low angle of tilt (10^o) and high angle of tilt (50^o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I_ON/I_OFF ratio, and the threshold voltage V_T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate-body voltage on DIBL, I_OFF, I_ON and the threshold voltage V_T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/I_D) and overall gain (gmR₀).     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

LaScO3 as a higher-κ dielectric for p-MOSFETs

The electrical properties of MOS capacitors with LaScO₃ thin films grown by molecular beam deposition (MBD) have been studied with and without post deposition annealing (PDA) in O₂ environment followed by forming gas. An EOT of 0.65 nm could be achieved for samples without PDA. However, the films suffer from large hysteresis and interface trap density. Applying PDA reduces the hysteresis, the D_it (down to the mid of 10¹¹ (eV cm²)⁻¹) and the leakage current by two orders of magnitude (down to the range of 10⁻⁴A/cm²) for an EOT of 1.1 nm. Furthermore we have successfully integrated LaScO₃ into FD MOSFETs on SOI substrates. The p-FETs with LaScO₃ show excellent characteristics with a steep subthreshold slope down to 65 mV/dec and hole mobilities comparable to HfO₂ and HfSiON.     

Charge trapping and interface characteristics in normally-off Al2O3/GaN-MOSFETs

Normally-off GaN-MOSFETs with Al₂O₃ gate dielectric have been fabricated and characterized. The Al₂O₃ layer is deposited by ALD and annealed under various temperatures. The saturation drain current of 330 mA/mm and the maximum transconductance of 32 mS/mm in the saturation region are not significantly modified after annealing. The subthreshold slope and the low-field mobility value are improved from 642 to 347 mV/dec and from 50 to 55 cm² V⁻¹ s⁻¹, respectively. The I_D-V_G curve shows hysteresis due to oxide trapped charge in the Al₂O₃ before annealing. The amount of hysteresis reduces with the increase of annealing temperature up to 750 °C. The Al₂O₃ layer starts to crystallize at a temperature of 850 °C and its insulating property deteriorates.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Highly (1 0 0)-oriented Pb(Zr0.20Ti0.80)O3/(Pb1−xLax)Ti1−x/4O3 multilayered thin films prepared by RF magnetron sputtering

The Pb(Zr_0.20Ti_0.80)O₃/(Pb_1−xLa_x)Ti_1−x/4O₃ (x = 0, 0.10, 0.15, 0.20) (PZT/PLT_x) multilayered thin films were in situ deposited on the Pt(1 1 1)/Ti/SiO₂/Si(1 0 0) substrates by RF magnetron sputtering technique with a PbO_x buffer layer. With this method, all PZT/PLT_x multilayered thin films possess highly (1 0 0) orientation. The PbO_x buffer layer leads to the (1 0 0) orientation of the multilayered thin films. The effect of the La content in PLT_x layers on the dielectric and ferroelectric properties of the PZT multilayered thin films was systematically investigated. The enhanced dielectric and ferroelectric properties are observed in the PZT/PLT_x (x = 0.15) multilayered thin films. The dielectric constant reaches maximum value of 365 at 1 KHz for x = 0.15 with a low loss tangent of 0.0301. Along with enhanced dielectric properties, the multilayered thin films also exhibit large remnant polarization value of 2P_r = 76.5 μC/cm², and low coercive field of 2E_c = 238 KV/cm.