Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics

N-type metal-oxide-semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37 nm has been demonstrated with La₂O₃ as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37 nm in EOT. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance.     

Degradation of high-K LA2O3 gate dielectrics using progressive electrical stress

The evolution of the leakage current in high-K lanthanum oxide films in MOS devices caused by the application of progressive electrical stress is investigated. The degradation method consists in performing successive voltage sweeps using an ever increasing voltage range with the aim of generating incremental damage to the structure in a controlled manner. We show that the total current flowing through the device can be thought of as formed by two parallel components, one associated with the tunneling mechanism and the other one associated with diode-like conduction. This latter component evolves with applied stress. It is shown the importance of considering series and parallel resistances in order to account for the right shape of the conduction characteristics. Analytical expressions for both current contributions suitable for all stages of degradation and bias conditions are provided.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

High-density MIM capacitors using Al2O3 andAlTiOx dielectrics

We have investigated the electrical characteristics of Al₂ O₃ and AlTiO_x MIM capacitors from the IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 μF/cm² are obtained for Al₂ O₃ and AlTiO_x MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiO_x MIM capacitor has very large capacitance reduction at increasing frequencies. In contrast, good device integrity has been obtained for the Al₂O₃ MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RFfrequency range

We have characterized the capacitance and loss tangent for high-k Al₂O₃ and AlTiO_x gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO₂ was demonstrated individually by the proposed Al₂O₃ and AlTiO_x gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO₂ from 100 KHz to 20 GHz. These results suggest that both Al₂O₃ and AlTiO_x are suitable for next generation MOSFET application into RF frequency regime     

Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics

Capacitors with ultra-thin (6.0-12.0 nm) CVD Ta₂O₅ film were fabricated on lightly doped Si substrates and their leakage current (I_g-V_g) and capacitance (C-V) characteristics were studied. For the first time, samples with stack equivalent oxide thickness around 2.0 nm were compared with ultra-thin silicon dioxide and silicon oxynitride. The Ta₂O₅ samples showed remarkably lower leakage current, which not only verified the advantages of ultra-thin Ta₂O₅ as dielectrics for high density DRAM's, but also suggested the possibility of its application as the gate dielectric material in MOSFET's     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

Demonstration of GaN MIS diodes by using AlN and Ga2O3(Gd2O3) as dielectrics

GaN MIS diodes were demonstrated utilizing AlN and Ga₂O₃(Gd₂O₃) as insulators. A 345 Å of AlN was grown on the MOCVD grown n-GaN in a MOMBE system using trimethylamine alane as Al precursor and nitrogen generated from a SVT RF N₂ plasma. For the Ga₂O₃(Gd₂O₃) growth, a multi-MBE chamber was used and a 195 Å oxide was E-beam evaporated from a single crystal source of Ga₅Gd₃O₁₂. The forward breakdown voltage of AlN and Ga₂O₃(Gd₂O₃) diodes are 5 and 6 V, respectively, which are significantly improved over 1.2 V from that of a Schottky contact. From the C–V measurements, both kinds of diodes showed good charge modulation from accumulation to depletion at different frequencies. The insulator/GaN interface roughness and the thickness of the insulator were measured with X-ray reflectivity.     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Effects of La2O3 incorporation in HfO2 gated nMOSFETs on low-frequency noise

The effect of La₂O₃ incorporation on the spatial trap distribution in HfO₂ gate dielectrics is investigated. The incorporation of La₂O₃ in HfO₂ dielectric has been found to improve the effective mobility in addition to reduced interface-state density. The trap distribution analysis in the HfO₂ layer extracted by combining the charge pumping (CP) method and the low-frequency noise (LFN) method has revealed significant reduction in the amount of traps at HfO₂/SiO₂-interlayer interface and in the HfO₂ layer by La₂O₃ incorporation.     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

Thin fluorinated gate dielectrics grown by rapid thermal processingin O2 with diluted NF3

The authors report the application of rapid thermal processing (RTP) to the fabrication of ultrathin (~10 nm) high-quality fluorinated oxides in O₂+NF₃ (100 ppm diluted in N₂). NF₃ was used as the F source gas and was introduced either prior to rapid thermal oxidation (RTO) or with O₂ during the initial stage of RTO. The oxidation rate was enhanced because of the presence of NF₃. In addition, F depth profiles in fluorinated oxides were dependent upon the process conditions. The electrical characteristics of MOS capacitors have been studied and correlated with the chemical properties. The initial interface state density (D_t) was found to decrease with F incorporation. The results suggest that the interfacial F incorporation plays a major role in determining the interface hardness for both hot-electron and radiation damages     

Distribution and generation of traps in SiO2/Al2O3 gate stacks

In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO₂/Al₂O₃ n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements performed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO₂ interface.     

Electrical and interfacial characteristics of nanolaminate (Al2O3/ZrO2/Al2O3) gate stack on fully depleted SiGe-on-insulator

The structural and electrical characteristics of a novel nanolaminate Al₂O₃/ZrO₂/Al₂O₃ high-k gate stack together with the interfacial layer (IL) formed on SiGe-on-insulator (SGOI) substrate have been investigated. A clear layered Al₂O₃ (2.5 nm)/ZrO₂ (4.5 nm)/Al₂O₃ (2.5 nm) structure and an IL (2.5 nm) are observed by high-resolution transmission electron microscopy. X-ray photoelectron spectroscopy measurements indicate that the IL contains Al-silicate without Ge atom incorporation. A well-behaved C–V behavior with no hysteresis shows the absence of Ge pileup or Ge segregation at the gate stack/SiGe interface.