Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Thinned wafer multi-stack 3DI technology

Wafer scale 3DI technology, so-called wafer-on-a-wafer (WOW), characterized by thinned-wafer stacking and Cu multi-level interconnects, has been developed, and revealed that seven-level multi-wafer stacking is possible. The WOW process differs from the chip-on-a-chip and chip-on-a-wafer processes and can be used for wafer-scale bulk processes, enabling manufacturing from transistor to 3D stacking using wafers. Wafers are thinned down to 20-μm and bonded to the base wafer following back-to-face stacking. Through-silicon-via (TSV) holes with a diameter of 30 μm are formed and etched-off until the lower electrode of Au which is patterned on the underneath wafer. Titanium (Ti) and titanium-nitride (TiN) are formed on a TSV hole as a barrier metal and electrode for the electrochemically plated Cu (ECP-Cu). After ECP-Cu deposition, surface planarization is performed using Surface Planer™. Those wafers are used as a base wafer and multi-stacking is carried out repeatedly. The vertical connection between Cu of TSV and Au is therefore connected with a self-aligned contact and without a bump electrode. The electrical properties of the 242-chain contacts within the wafer were measured and no open failure was found. Adopting the thinned substrates eliminates deep silicon etching, and TSV filling which take a long process time, and reduces the residual stress on the Cu plug. Wafers can be stacked as much as possible in accordance with the degree of integration, and this is expected to be a low-cost and high-integration technology for post-scaling.     

PECVD oxide as intermediate film for wafer bonding: Impact of residual stress

The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD oxides are systematically analysed for various deposition conditions and post-anneal treatments. Rapid thermal anneal (RTA) at a temperature over 900 °C for 15 s is proven to be the most efficient to reduce the residual stress in the film and its etch rate in BHF solution, as well as to enhance its long term stability. The reduction of the internal stress in PECVD oxide is mandatory to minimize the wafer bow which degrades the wafer bonding quality. Bonded samples show that the resulting surface energy tends to vary inversely with the elastic energy stored by the conformation of the wafers during the direct bonding. About 45 μm wafer bow (3 inch wafer, 380 μm-thick) comes out as an upper bow limit, preventing direct bonding to occur. The use of a RTA step following the PECVD oxide layer deposition is demonstrated to be an efficient technological solution to minimize the wafer bow and thus maximize the bonding surface toughness. The experimental results presented in this paper highlight the importance of monitoring the residual stress in intermediate oxide layers to assure high quality and reliable bonding and thus future three-dimensional integration.     

Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias

Three-dimensional (3D) integration is emerging as an attractive technology to continue Moore’s law through the integration of multi-stacked chips interconnected with through-silicon-vias (TSVs). To address the challenge in filling high aspect-ratio TSVs with copper, this paper reports an improved bottom-up copper electroplating (BCE) technique by introducing a glass transfer wafer, which is temporarily bonded with the device wafer to provide a copper seed layer. As the copper seed layer on the transfer wafer covers the through-holes, copper is electroplated from the bottom seed layer to the top opening of the through-holes without forming any voids or seams. This avoids the time consuming sealing process in conventional BCE, which normally takes 3-5 h. Thanks to the mechanical support of the transfer wafer, the device wafer can be thinned to several tens of micrometers. Using this technique, TSVs with diameter of 5 μm and aspect-ratio of 13:1 have been achieved. Based on the improved BCE technique, a through-via type 3D integration strategy is developed.     

Effect of additive N2 and Ar gases on surface smoothening and fracture strength of Si wafers during high-speed chemical dry thinning

In this work, we investigated the changes in the surface roughness and fracture strength of bare or mechanically ground Si wafers caused by high-speed chemical dry etching. High-speed chemical dry thinning was achieved by injecting NO gas and additive N₂ and Ar gases directly into the reactor during the supply of F radicals from NF₃ remote plasmas. With the additional injection of N₂ and Ar gases, together with the direct-injected NO gas, the rough surfaces of the mechanically ground Si wafers could be effectively smoothened while keeping the thinning rate of Si very fast, viz. up to 18.2 μm/min. The additive N₂ gas reduced the wafer surface temperature after thinning. The fracture strength of the Si wafers thinned down to 50 μm by the chemical dry etching process was more highly increased, due to the more effective removal of the mechanical damage and stress generated during the mechanical grinding process, as compared to the other final thinning methods such as lapping or plasma etching. The results indicated that the high-speed dry chemical thinning process could be used for the ultra-thin final thinning of Si wafers for next generation three-dimensional packaging technologies.     

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

CMOS compatible bistable electromagnetic microvalve on a single wafer

This paper presents our work in the bistable electromagnetic actuated microvalve. The microvalve is entirely fabricated by surface micromachining on top of a single Si (silicon) substrate. The microvalve has an overall diameter of 1600 μm and the overall height of 600 μm, including the wafer thickness. The bistable mechanism is achieved by integrating an electroplated micro CoNiMnP magnet on the membrane. The microvalve was tested in the flow of deionized (DI) water at 0-50 μL/min. The latching/unlatching of the microvalve was performed to control the flow DI water at 30 μL/min, it required the operational current of 0.38 A and the power of 1.17 W. The latching/unlatching response time of the microvalve is 10 ms, with the leaking rate of 0.16-0.8 μL/min.     

Spray coating of PMMA for pattern transfer via electron beam lithography on surfaces with high topography

Spray coating of polymethylmethacrylate (PMMA) as electron beam resist on non planar surfaces is presented as a reliable technique for deposition of uniform resist layers with adjustable thickness at wafer scale. In the experiments a commercial spray coating system with an ultrasonic spray nozzle was used. Parameters which influence the quality of the resist layer with respect to uniformity across a 4 in Si wafer, such as ultrasonic power and dispensed volume, were evaluated. The suitability of spray coated PMMA for the pattern transfer on surfaces with high topography was proven by PMMA spray coating of 8 μm deep trenches etched into Si wafers. The PMMA was then electron beam exposed and chromium line patterns were transferred on the Si surface via a lift-off process.     

Study of electrochemical etch-stop for high-precision thickness control of single-crystal Si in aqueous TMAH : IPA : pyrazine solutions

In this paper, we describe a method of controlling the thickness of single-crystal Si membranes, fabricated by wet anisotropic etching in aqueous tetramethyl ammonium hydroxide (TMAH) : isopropyl alcohol (IPA) : pyrazine solutions. The Si surface of the etch-stopped microdiaphragm is extremely flat with no noticeable taper or nonuniformity. The benefits of the electrochemical etch-stop method for the etching of n epilayer-embedded p-type single-crystal Si(0 0 1) wafers in aqueous TMAH became apparent when the reproducibility of the microdiaphragm’s thickness in mass production was realized. The results indicated that the use of the electrochemical etch-stop method for the etching of Si in aqueous TMAH provided a powerful and versatile alternative process for the fabrication of high-yield Si microdiaphragms (20 ± 0.26 μm s.d). With etch-stop, the pressure sensitivity of devices fabricated on the same wafer can be controlled to within ±2.3% s.d.     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.     

Impact of electroplated copper thickness on copper CMP and Cu/Coral™ BEOL integration

A study was carried out to establish the impact of electrochemical plated (ECP) Cu thickness on the effect of dishing during Cu chemical mechanical planarization and the electrical and reliability performance of 0.13 μm Cu/Coral devices. The roughness of Cu films at the wafer edge was found to increase with increasing film thickness while it remained constant at the wafer centre. This resulted in different Cu grain morphology across the wafers. The reduction in sheet resistance (R_s) for the Cu film after annealing, as well as the as-deposited and post annealed film stresses were also found to be dependent on the ECP Cu thickness. As the thickness increased, the R_s reduction increased while the as-deposited and post annealed film stresses decreased. The different ECP Cu thickness did not show any significant difference in the amount of Cu dishing at the centre of the wafers. However, at the wafer edge, the Cu dishing amount was found to be significantly affected by the Cu thickness in which the amount of dishing increased as the thickness increased. The via chain, Kelvin via, M1 line and M2 line resistances also showed a strong dependence on the ECP Cu thickness. The thinnest Cu film of 0.7 μm gave the lowest results with the tightest spread for the four resistances tested. For the via chain and M1 line resistance, it was followed by the 1.0 μm Cu film and the 1.3 μm film yielded the worst data. In the case of Kelvin via and M2 line resistance, the thicker plated Cu films gave similar worse results. All the electrical results showed good coincidence with the Cu dishing data. The voltage ramp (v-ramp) data showed no significant difference in the electrical field leading to dielectric breakdown at both M1 and M2 lines for all the three types of ECP Cu thickness split.     

Room-temperature CW operation of InGaAsP lasers on Si fabricated by wafer bonding

1.3-/spl mu/m InGaAsP-InP lasers have been successfully fabricated on Si substrates by wafer bonding with heat treatment at 400/spl deg/C. A pressure of 4 kg/cm/sup 2/ has been applied on the wafers before the heat treatment and this pressure application has enabled us to achieve bonding strength required for the device fabrication even when the bonding temperature is as low as 400/spl deg/C. Room-temperature continuous-wave operation with threshold current of 49 mA has been achieved for 7-/spl mu/m-wide mesa lasers.     

铌酸锂晶片的键合减薄及热释电性能研究

铌酸锂(LN)作为一种热释电材料,可以被用于制作光电探测器敏感单元的敏感层,但通常LN晶片厚度为0.5 mm,远大于光电敏感单元厚度的要求,所以需要用键合减薄及抛光技术对LN晶片进行加工处理。本研究所用键合减薄技术主要包含:RZJ-304光刻胶键合、铣磨、抛光、剥离液剥离和丙酮清洗RZJ-304胶。利用该技术加工得到了面积为10 mm×10 mm,厚度为50μm,表面比较光滑,表面粗糙度为1.63 nm的LN晶片。LN晶片的热释电信号峰峰值在减薄抛光后为176 mV,是未经处理时的4倍,满足了热释电探测器敏感层的要求。     

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".     

RF device package method using Au to Au direct bonding technology

This paper presents design, fabrication and evaluation of a wafer level MEMS (Micro Electro Mechanical System) encapsulation using an Au to Au direct bonding with wrinkle patterned layer. For the effective encapsulation, the optimal bonding condition, the bonding temperature 350 °C, the bonding pressure 58 MPa and the duration time 30 min, was developed and used in this paper. We briefly evaluated the bonding strength of test wafers after the bonding test. For RF (Radio Frequency) device packaging, we effectively interconnected Au CPW (Coplanar Waveguide) lines to feedthroughs and measured the RF characteristics. Measured insertion loss of the packaged CPW line was −0.11 dB at 2 GHz. The glass wafer having patterned Au sealing lines was also bonded and has been dipped in the acetone solution for 24 h to examine the leakage of bonding wafer. After 24 h dipping, any leakage point has not been observed at the sealing line and inside the cavity. These results showed that our Au to Au direct bonding method is very reliable and suitable for RF device packaging.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Bonding silicon wafer to silicon nitride with spin-on glass as adhesive

Using spin-on glass (SOG) as an adhesive, an Si wafer with thermal oxide was successfully bonded to one with an RF-sputtered Si3N4 film. This ensures that SOG films are effective in bonding Si wafers to less reactive surfaces than Si or SiO2 such as silicon nitride. It was also found that the previously reported bonding procedure can be simplified by suppressing the spin-induced radial striations of the SOG films.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

Miniature SAW device using MEMS technology

A miniature SAW device is designed and fabricated at 1 GHz for wireless communication system. A 5 μm thin film of ZnO is successfully deposited using RF sputtering technique on plasma-enhanced chemical deposition (PECVD) SiO₂ layer of 1 μm on top of Si wafer under various operating conditions. The c-axis-oriented ZnO film exhibit a sharp diffraction peak corresponding to the (0 0 2) reflection at 2θ=34.42. The fabrication process utilizing the micro-electro-mechanical systems (MEMS) technology of the SAW device is described. Simulation of the RF-SAW filter is performed. Measurements and experimental work are presented for the RF-SAW device.