Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

New implementation of high linear LNA using derivative superposition method

New implementation of a high linear low-noise amplifier (LNA) using the improved derivative superposition (DS) method is proposed. The input stage is formed by two transistors connected in parallel. One transistor is biased in the strong inversion region as usual and another one is biased in the moderate inversion region instead of the weak inversion region, thus allowing a feasible source degeneration inductance at the sources of the two transistors to achieve a good input impedance matching and low noise figure (NF) while keeping high third-order input intercept point (IIP3) improvement with the DS method. The new implementation has been used in a 0.18-μm CMOS high linear LNA. The measured results show that the LNA achieves +11.92 dBm IIP3 with 9.36 dB gain, 2.25 dB NF and 7.5 mA at 1.8 V power consumption.     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

A SiGe LC-ladder low noise amplifier with base resistance match,gain and noise flatness for UWB applications

This study presents a 3.1–10.6 GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18 µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S₂₁) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33 mW power and achieves S₂₁ of 20.65+0.7 dB, NF of 2.79+0.2 dB over the band of 3.1–10.6 GHz. The simulated input third-order intermodulation point (IIP3) is −17 dBm at 10 GHz.     

Image-rejection CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

Image-rejection receiver using on-chip active notch filters for 2.4-GHz band wireless communication applications

This paper presents the design and experimental results of image-rejection (IR) receiver front-end for 2.4-GHz band applications. The proposed IR-receiver front-end integrates a third-order active notch filter into each of conventional cascode low noise amplifier and down-conversion mixer to achieve high image-rejection ratio (IRR). The image signal is suppressed and the wanted signal is maximized due to series and parallel resonator effects of the notch filter, respectively. Consequently, the proposed IR-receiver front-end implemented in a standard 0.18 μm CMOS technology has the power gain of 21.5 dB, the noise figure of 3.5 dB, the input third order intermodulation product of ?15 dBm and the IRR of 56 dB. The IR-receiver front-end dissipates a total of 5.5 mA from supply voltage of 1.8 V.     

A SiGe HBT low noise amplifier using on-chip notch filter for K band wireless communication

In this paper a new notch filter topology has firstly been described. In order to improve the input match as well as enhance the gain on the operating frequency of 20.5 GHz, extra capacitor has firstly been added in the passive base-collector notch filter forming a new scheme, eliminating the operating-frequency (op) input mismatch in formal base-collector notch filters. EM simulations have shown that the LNA obtained 14.1 dB gain at 20.5 GHz and high image-rejection ratio (IRR) of 33.5 dB at image frequency of 15 GHz, and S₁₁ of -15 dB was obtained compared to −8 dB without notch filter at operating frequency, NF was below 5 dB at gain peak frequency, power consumption was 18 mW at 3 V voltage supply, and IIP3 was 3.43 dBm ensuring a high linearity in SiGe bipolar process.     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.     

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm², including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.     

Low-power highly linear UWB CMOS mixer with simultaneous second- and third-order distortion cancellation

A 3.1-4.8 GHz mode-1 UWB CMOS mixer that utilizes simultaneous second- and third-order distortion cancellation is presented. The scheme is based on a new derivative superposition, employing PMOS as an auxiliary FET to cancel the second- and the third-order nonlinear currents of common-source transconductance in the mixer and gives rise to low-distortion operation for a broad range of gate-source voltage. Full Volterra series analysis of the proposed transconductance is reported to examine the effectiveness of the new technique. Simulations in a 0.13 μm CMOS technology demonstrate that IIP3 and IIP2 of the proposed mixer have 18 and 10 dB improvements, respectively, compared with conventional Gilbert-type mixer with the same power consumption. The robustness of the technique has been verified by Monte Carlo analysis. The mixer has a gain of 12 dB and noise figure of 13 dB, while drawing only 2.5 mA from 1.2 V supply voltage.     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

可调节镜像电流源的研究及其在LNA中应用

A novel topology of current mirror （CM） with tunable output current is proposed. Two methods for output current tuning are presented. The first one utilizes an analog input voltage for linear current output, and the second one has an N-bit digital input signal for 2N un-continuous current outputs. A linearization method for low noise amplifier （LNA） is proposed and realized with this tunable CM. As the provider of the bias current, the CM has brought the LNA a lower NF （noise figure） and a higher IIP3 （input-referred third-order intercept point） compared with a conventional one. The experimental results show that the LNA achieves 1.47 dB NF and ＋ 19.83 dBm IIP3 at 860 MHz.     

Tunable current mirror and its application in LNA

A novel topology of current mirror (CM) with tunable output current is proposed. Two methods for output current tuning are presented. The first one utilizes an analog input voltage for linear current output, and the second one has an N-bit digital input signal for 2~N un-continuous current outputs. A linearization method for low noise amplifier (LNA) is proposed and realized with this tunable CM. As the provider of the bias current, the CM has brought the LNA a lower NF (noise figure) and a higher IIP3 (input-referred third-order intercept point) compared with a conventional one. The experimental results show that the LNA achieves 1.47 dB NF and + 19.83 dBm IIP3 at 860 MHz.     

Low-power current-reused RF front-end based on optimized transformers topology

This paper discusses the design, analysis and performance of a 2.4 GHz fully integrated low-power current-reused receiver front-end implemented in 0.18 μm CMOS technology. The front-end is composed of a single-to-differential low-noise amplifier (LNA), using high-Q differential transformers and inductors and a coupled switching mixer stage. The mixer transconductor and LNA share the same DC current. Measurements of performance show a conversion gain of 28.5 dB, noise figure of 6.6 dB, 1 dB compression point of −32.8 dBm and IIP3 of −23.3 dBm at a 250 kHz intermediate frequency, while dissipating 1.45 mA from a 1.2 V supply.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

A low-noise mixer with an image-reject notch filter for 2.4 GHz applications

This paper presents a low noise first down-conversion mixer with a notch filter for the heterodyne receiver. The notch filter connected to the output node of the mixer driver stage plays a role of image rejection at an image frequency, thereby suppressing the sideband image noise and improving the mixer noise performance. Targeted for 2.4 GHz industrial-scientific-medical band applications, a simple source-degenerated down-conversion single balanced mixer with the filter is implemented. The measurement results of the proposed down-conversion mixer shows about 3.0 dB improvement of single-side band noise figure, about 2.9 dB power conversion gain improvement, and 25 dB image suppression compared to those without the filter dissipating 4 mA from a 2.5 V supply voltage.     

High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.